SoC UPF Methodology Engineer

Austin, TX, US • Posted 9 hours ago • Updated 9 hours ago
Full Time
On-site
Fitment

Dice Job Match Score™

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Job Details

Skills

  • System On A Chip
  • NAT
  • Integrated Circuit
  • NAND
  • Art
  • Management
  • Place And Route
  • Workflow
  • Scripting
  • Python
  • Tcl
  • CMOS
  • Artificial Intelligence
  • Machine Learning (ML)
  • Workflow Optimization
  • RTL
  • Communication
  • Collaboration

Summary

Are you passionate about crafting solutions to intricate challenges? Join the Low Power group\\nat Silicon Technologies and contribute to the development of cutting-edge technology and\\ncapabilities for low-power chip design. Your work will fuel Apple's next-generation chips!\\nYou'll play a crucial role in exploring AI/ML to design the workflow for the next generation of\\nUPF. Additionally, you'll refine our existing UPF framework and ensure its seamless integration\\nand rigorous verification across our mobile products.

In this role, your main objective will be to enhance our Unified Power Format (UPF)\nmethodologies, refining power intent specification, execution, and validation to support state-\nof-the-art mobile SOCs. Key responsibilities encompass:\n Enhancing power intent coverage via advanced static and dynamic verification techniques.\n Developing tailored UPF solutions to align with unique project requirements.\n Overseeing UPF deployment and sign-o? for frontend (FE) and place-and-route (P&R) stages.\n Conducting thorough power intent assessments on custom circuitry.\n Partnering with design and verification teams to troubleshoot and fix UPF-related workflow\nchallenges.\n Integrating AI/ML technologies to optimize UPF processes and methodologies.

A minimum of a bachelor's degree in relevant field and a minimum of 10 years of relevant industry experience

Expertise in UPF implementation and verification.\nProficiency in scripting with languages like Python and Tcl.\nUnderstanding of CMOS power design principles.\nExperience applying AI/ML to coding and workflow optimization.\nKnowledge of multi-voltage static verification tools (e.g., VSILP/VCLP, CLP).\nFamiliarity with the complete RTL-to-GDSII design flow.\nStrong communication abilities for e?ective collaboration across multidisciplinary teams.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 90733111
  • Position Id: 4c246737f83b11065c84eae8cc4bcf42
  • Posted 9 hours ago
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