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AI Data Center High-Speed Interconnect Architect
Direct Hire - Full Time
Fremont, CA (Onsite)
Salary: $220k-$350k
Job Summary
The High-Speed Interconnect Architect will define, develop, and optimize next generation interconnect architectures for advanced AI servers and rack scale systems. This role focuses on technologies such as high speed backplanes (NVLINK, UALINK), co packaged copper, PCIe, CXL, OSFP/OSFP X optics, 448G/lane signaling, and advanced onboard connector systems. The architect ensures exceptional bandwidth, latency, signal integrity, power efficiency, and scalability within dense AI and HPC data center environments.
Success in this role requires strong cross functional collaboration and engagement with industry standards bodies to influence future interconnect technologies. This position is foundational to enabling scalable, high performance AI infrastructure.
Essential Duties & Responsibilities
Architectural Design & Optimization
- Define and optimize high speed interconnect architectures including backplanes, co packaged copper, cables, OSFP/OSFP X, onboard connectors, and next gen link technologies.
- Balance performance, signal integrity, power, thermals, cost, density, and manufacturability.
Technology Assessment
- Evaluate and select interconnect standards and protocols (NVLINK, UALINK, PCIe, CXL, Ethernet, InfiniBand) aligned with roadmap requirements and long term scalability.
Signal & Power Integrity
- Partner with SI/PI engineering teams to ensure robust high speed signaling compliant with electrical, EMI/EMC, and mechanical constraints.
Cross Functional Integration
- Collaborate with hardware, system, mechanical, packaging, firmware, and software teams to integrate interconnect solutions into AI server architectures and rack scale designs.
Industry Standards Participation
- Represent the company in OCP, PCI SIG, UALINK Consortium, IEEE, and CXL Consortium.
- Contribute to next generation interconnect standards and track industry technology trends.
Client & Partner Engagement
- Interface with hyperscalers, OEMs, silicon vendors, and interconnect partners to gather requirements, resolve challenges, and jointly develop new solutions.
Documentation & Roadmapping
- Produce specifications, architecture documents, design guidelines, and contribute to product and technology roadmaps.
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
- 5+ years of experience in high speed interconnect architecture, signal integrity, or system design within compute, networking, or AI platforms.
- Deep expertise in high speed protocols and link technologies: NVLINK, UALINK, PCIe, CXL, Ethernet, InfiniBand, OSFP/OSFP X, and emerging 100G-448G/lane signaling.
- Strong knowledge of SI/PI principles, PCB/package/system design, and simulation tools (HFSS, ADS, Sigrity, etc.).
- Experience influencing or contributing to industry standards bodies.
- Excellent communication and cross functional leadership skills.
- Familiarity with hardware/software co design, platform performance analysis, or AI/HPC workloads is a plus.
All qualified applicants will receive consideration for employment without regard to race, color, national origin, age, ancestry, religion, sex, sexual orientation, gender identity, gender expression, marital status, disability, medical condition, genetic information, pregnancy, or military or veteran status. We consider all qualified applicants, including those with criminal histories, in a manner consistent with state and local laws, including the California Fair Chance Act, City of Los Angeles' Fair Chance Initiative for Hiring Ordinance, and Los Angeles County Fair Chance Ordinance.
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