Design Engineer

Austin, TX, US • Posted 4 days ago • Updated 4 days ago
Full Time
No Travel Required
On-site
Depends on Experience
Fitment

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Job Details

Skills

  • ASIC
  • DFT
  • Python
  • VLSI
  • ICC
  • Debugging
  • Static Timing Analysis

Summary

Avanciers are looking for a skilled Physical Design Engineer with hands-on experience in backend VLSI design for ASICs/SoCs. The role involves block-level and top-level physical design implementation including floorplanning, placement, CTS, routing, timing closure, and signoff activities.

Key Responsibilities

  • Floorplanning, placement, CTS, routing, and timing closure
  • Power planning, IR drop, and signal integrity analysis
  • Chip-level integration and physical verification
  • Support netlist-to-GDSII implementation flow
  • Work closely with DFT and front-end teams
  • Develop automation scripts using Tcl/Perl/Python/Shell

Required Skills

  • 5–18 years of ASIC/SoC Physical Design experience
  • Strong knowledge of STA, CTS, routing, and signoff flows
  • Hands-on experience with Innovus, ICC2, PrimeTime, Calibre
  • Strong scripting and debugging skills
  • Experience with advanced technology nodes preferred

Note: Only candidates with 5–18 years of experience will be considered.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 91094911
  • Position Id: 8970764
  • Posted 4 days ago
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