Design Verification Engineer

Requirements

• Knowledge of semiconductor ASIC design/verification methodologies and flows

• Working knowledge of Verilog/SystemVerilog/UVM

• Strong programming skills including object-oriented programming

• Working experience with digital logic design and verification

• Practical experience in D2D, NOC, AXI, Ethernet, DDR/LPDDR, HBM, Security, Networking, ARM CPU subsystems

• Demonstrates good analysis, problem-solving, and critical thinking skills

• Effective interpersonal, teamwork, and communication skills

• BS/MS degree in EE/CE or related technical field(s) is required

Job Responsibilities

• Work with design engineers on the verification of an IP, subsystem, SOC, or chiplet

• Write block-level test plans to verify the functionality of a block or subsystem

• Develop UVM environments and tests that comply with coding guidelines

• Help write scripts as needed to automate tasks

• Write functional coverage items and close coverage buckets

• Strong debug skills

• Help to monitor regressions and triage as needed

• Assist in checklist closure