Signal Integrity Engineer

Introduction:

An experienced Signal Integrity Engineer with at least 5 years of experience is needed to support high-speed interface development and validation. The engineer will be working on cutting-edge technologies such as LPDDR5X, PCIe Gen7, and UCIe (64G).

Responsibilities:

• Perform channel modeling, extractions, and eye analysis for high-speed interfaces.
• Conduct pre- and post-layout simulations to ensure compliance with interface standards.
• Analyze crosstalk, reflections, jitter, and insertion/return loss.
• Collaborate with design, package, and PCB teams to optimize SI performance.
• Generate reports and recommendations to support design decisions.

Requirements:

• Strong background in signal integrity for high-speed serial and memory interfaces.
• Hands-on experience with HFSS or Clarity, Siwave or PowerSI, SystemSI or ADS or AEDT.
• Familiarity with JEDEC/LPDDR5/6 and PCIe/UCIe standards.
• Strong problem-solving skills and ability to work across cross-functional teams.