DFT Engineer

Position Overview

As a DFT Engineer, you will be responsible for defining, implementing, and executing comprehensive Design-for-Test (DFT) strategies for high-performance SoCs and ASICs.

You will collaborate closely with RTL design, physical design, verification, product engineering, and silicon validation teams to ensure high test coverage, silicon quality, and efficient manufacturing test enablement.

Key Responsibilities

1. Pre-Silicon DFT Implementation

• Define and implement DFT architectures, including Scan, ATPG, MBIST, and JTAG.
• Perform scan insertion, scan chain stitching, and optimization.
• Implement scan compression architectures such as EDT/SmartTest.
• Integrate MBIST controllers, memory repair mechanisms, and test routines.
• Generate and debug ATPG patterns, including Stuck-at, Transition, At-speed, and Path Delay testing.
• Perform gate-level simulations using Verilog/SystemVerilog and SDF.
• Execute DFT rule checking, linting, and design validation.

2. Post-Silicon Validation and Production Support

• Convert ATPG and MBIST patterns into tester-compatible formats such as STIL and WGL.
• Support first-silicon bring-up and debug DFT-related issues.
• Troubleshoot ATPG pattern failures and silicon test issues.
• Collaborate with Product and Test Engineering teams to improve test coverage, reduce test time, and enhance manufacturing yield.

Required Technical Skills

• Strong hands-on experience in Design-for-Test (DFT) for SoC/ASIC designs.
• Expertise in Scan Insertion, Scan Stitching, and Scan Compression.
• Strong ATPG experience, including Stuck-at and At-speed fault models.
• Hands-on experience with MBIST architecture, insertion, and memory repair.
• Good understanding of JTAG and IEEE 1149.1 standards.
• Proficiency in Verilog/SystemVerilog and gate-level simulation.
• Experience with industry-standard DFT tools such as:
  • Siemens Tessent
  • Synopsys TetraMAX
  • Cadence Modus
  • SpyGlass DFT

Preferred Qualifications

• Proficiency in Tcl, Python, or Perl scripting.
• Knowledge of Synopsys Design Compiler or Cadence Genus.
• Understanding of Static Timing Analysis (STA) and DFT-mode constraints.
• Exposure to High-Speed I/O testing, SerDes loopback, and Analog DFT.
• Experience with ATE pattern conversion and post-silicon production support.