Lead Product Engineer

Benefits: Day-1 Onsite Competitive salary Opportunity for advancement DFT Engineer (Design for Test) Location: Santa Clara, CA (Onsite) Employment Type: Long-Term Contract Interview Process: Virtual Interviews Compensation: Based on Experience (DOE) Engagement: ANY Preference: Local candidates or those able to work onsite We are seeking an experienced DFT Engineer to join a high-performing ASIC/SoC engineering team. In this role, you will be responsible for designing and implementing De

Job Title: DFT Engineer Location: Santa Clara, CA Work Arrangement: Onsite Experience: 5+ Years JOB DESCRIPTION We are seeking an experienced DFT Engineer to join a cutting-edge Silicon Engineering team working on next-generation GPU and AI products. The ideal candidate will have strong expertise in Design for Test (DFT) architecture, scan, MBIST, LBIST, JTAG, ATPG, and silicon debug. This is an excellent opportunity for a hands-on DFT Engineer to contribute to complex ASIC/SoC designs and next-

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Principal DFT Engineer Broadcom's ASIC Product Division is seeking candidates for a DFT position at our San Jose, California, Development Center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT spe

Position:Design For Test Engineer (IC) Job Description:What You\'ll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Sh