Staff Full-Chip Timing Engineer

Looking for an Innovative Staff Full-Chip Timing (STA) Engineer - On Site

This Jobot Job is hosted by: Lindsey Cusic
Are you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume.
Salary: $175,000 - $235,000 per year

A bit about us:

We are a growing semiconductor design organization focused on advanced ASIC and SoC development. Our team is built around deep technical expertise, fast execution, and a strong ownership mindset.

We work on complex, high-performance silicon solutions that require tight cross-functional collaboration across physical design, timing, architecture, and verification. As we continue scaling our engineering team in the Bay Area, we are looking for experienced contributors who thrive in technically challenging, execution-focused environments.

Why join us?

Work on advanced-node silicon programs with real tapeout ownership
Join a technically strong, highly collaborative engineering culture
High-impact role with visibility across design and signoff stages
Onsite collaboration with experienced physical design and architecture teams
Competitive compensation aligned with Bay Area semiconductor market
Opportunity to influence methodology and drive execution standards

This is a role for engineers who want to own outcomes - not just support tasks.

Job Details

We are seeking a Staff Full-Chip Timing Engineer to lead static timing analysis and signoff closure at the top level of complex ASIC/SoC programs.

Responsibilities:
Own full-chip static timing analysis from synthesis through signoff
Drive timing closure across multi-mode, multi-corner (MMMC) environments
Perform deep analysis using PrimeTime (or equivalent)
Identify and implement ECO timing fixes
Collaborate closely with Physical Design, CTS, Synthesis, and Architecture teams
Support advanced-node tapeouts (7nm/5nm and below preferred)
Contribute to timing methodology and flow improvements

Qualifications:
8+ years of semiconductor industry experience
Demonstrated ownership of full-chip STA and signoff timing closure
Strong expertise in PrimeTime (Tempus experience a plus)
Experience working on advanced technology nodes
Solid understanding of CTS, setup/hold analysis, OCV/AOCV, and crosstalk
Strong scripting skills (Tcl required; Python a plus)
Experience supporting successful tapeouts

Location:
Onsite - San Jose, CA

Compensation:
$185,000 - $235,000 base salary (commensurate with experience)

Interested in hearing more? Easy Apply now by clicking the "Apply Now" button.

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