Analog Design Engineer

Job Title: SerDes Design Engineer (Mid-level / Senior)
Location: San Francisco, CA (Hybrid/Onsite)
Experience: 5 12+ years

Job Description

We are looking for an experienced SerDes Design Engineer to join our high-speed I/O design team in San Francisco. The candidate will work on the design and development of advanced high-speed serial interfaces for next-generation semiconductor products.

Responsibilities

• Design and develop high-speed SerDes PHY architectures (TX/RX, PLL, CDR)
• Work on equalization techniques such as CTLE, DFE, FFE
• Perform circuit design, simulation, and verification in deep submicron CMOS technologies
• Support system-level integration and silicon bring-up
• Analyze signal integrity, jitter, and eye diagrams
• Collaborate with digital, layout, and validation teams
• Contribute to product debugging and performance optimization

Required Qualifications

• Bachelor s or Master s degree in Electrical Engineering or related field
• 5+ years (Mid-level) or 8+ years (Senior) of experience in SerDes / High-Speed IO design
• Strong knowledge of analog and mixed-signal circuit design
• Experience with protocols such as PCIe, Ethernet, USB, SATA, or DisplayPort
• Hands-on experience with Cadence/Synopsys tools
• Understanding of signal integrity and high-speed communication theory

Preferred Qualifications

• Experience with advanced process nodes (7nm/5nm/3nm)
• Silicon validation and lab bring-up experience
• Scripting skills (Python/Matlab) for modelling and analysis
• Prior work on production SerDes IP