Principal Test Development Engineer

Irvine, CA, US • Posted 1 day ago • Updated 8 hours ago
Full Time
On-site
USD $138,400.00 - 204,800.00 per year
Fitment

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Job Details

Skills

  • Cloud Computing
  • Innovation
  • Test Methods
  • Expect
  • Test Strategy
  • Root Cause Analysis
  • Interfaces
  • Computer Hardware
  • Drive Testing
  • Collaboration
  • Product Engineering
  • NPI
  • DFT
  • Roadmaps
  • Electrical Engineering
  • Computer Engineering
  • Semiconductors
  • Quality Assurance
  • Mixed-signal Integrated Circuit
  • SERDES
  • Testing
  • Debugging
  • Failure Analysis
  • Optimization
  • C
  • C++
  • Python
  • Perl
  • Automated Testing
  • Data Analysis
  • IT Management
  • IP
  • Intellectual Property
  • Economics
  • Manufacturing
  • Management
  • Mentorship
  • Leadership
  • Finance
  • Help Desk
  • Transcription
  • Communication
  • Real-time
  • Artificial Intelligence
  • Training
  • Recruiting
  • Law
  • Licensing

Summary

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Role Summary

A Principal Test Engineer is a senior technical leader responsible for defining, architecting, and driving end-to-end ATE test solutions across silicon bring-up, characterization, qualification, and high-volume production. This role combines deep hands-on expertise, cross-functional technical leadership, and strategic ownership of test methodology, infrastructure, and test economics.

What You Can Expect

Technical Leadership & Ownership
  • Serve as the technical owner for test strategy and execution across one or more complex silicon programs or technology domains.
  • Architect scalable ATE test solutions for wafer sort and final test on platforms such as Advantest 93K and/or Teradyne.
  • Lead new silicon bring-up, debug, and root-cause analysis across silicon, package, probe, hardware, and test program layers.
  • Define and drive test methodologies and best practices across teams and products.

Test Program & Infrastructure Development
  • Lead development and release of:
    • Characterization test programs
    • Qualification test programs
    • Production test programs
  • Optimize test time, coverage, yield, and cost, balancing quality and manufacturing efficiency.
  • Design and review high-speed ATE load boards, probe cards, and test interfaces in collaboration with hardware teams.
  • Drive test pattern conversion from simulation to ATE and ensure correctness and coverage.

Yield, Quality & Production Excellence
  • Analyze production data to identify systemic yield or quality issues and drive corrective actions.
  • Collaborate closely with Product Engineering, Design, DFx, Ops, and Manufacturing teams to resolve yield detractors.
  • Support production ramps, NPI milestones, and field issues with urgency and technical rigor.

Cross-Functional & Organizational Impact
  • Act as a technical authority and escalation point within Test Engineering.
  • Lead design-for-test (DFT) and testability reviews with design teams.
  • Mentor and guide senior and junior engineers; raise overall technical bar of the organization.
  • Influence roadmap decisions related to test infrastructure, platforms, and automation.

What We're Looking For

Required Qualifications
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • Typically 10+ years of semiconductor test engineering experience.
  • Deep expertise in:
    • ATE test development (Advantest 93K / Teradyne)
    • High-speed digital, analog, mixed-signal, or SerDes testing
    • Test program architecture, debug, and optimization
  • Strong skills in silicon debug, failure analysis, and yield optimization.
  • Programming proficiency (e.g., C/C++, Python, Perl) for test automation and data analysis.

Preferred / Differentiating Skills
  • Proven technical leadership across multiple programs or platforms
  • Experience defining standardized test frameworks or reusable IP
  • Strong understanding of test economics and manufacturing constraints
  • Ability to influence across organizations without direct authority
  • Track record of mentoring engineers and driving engineering excellence

Career Impact
  • High-visibility technical role with broad influence
  • Drives foundational decisions that affect product quality, cost, and time-to-market
  • Acts as a feeder role to Distinguished Engineer, Technical Fellow, or senior leadership paths

Expected Base Pay Range (USD)
138,400 - 204,800, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 10114994
  • Position Id: 4a3724b774d65dffcbf58780c4b0adc
  • Posted 1 day ago
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