Dv Engineer

"Exciting opportunity alert! 🚀 A leading supplier of state-of-the-art SoC and embedded IP is hiring for a Verification Engineer to join their high-performance design team! 💻

Responsibilities include:

- Developing verification environments using System Verilog and UVM
- Designing verification components and behavioral models
- Implementing coverage and assertions
- Debugging simulation failures and analyzing coverage results

Requirements:

- Bachelor's degree in EE, CS, or equivalent
- 12+ years of industry experience in verification
- Expertise in System Verilog, UVM, and RTL verification methodologies
- Strong programming skills in C/C++, Perl, and scripting

Nice to haves:

- Experience with Emulators and FPGA-based prototyping
- Knowledge of CPU, DDR, Bus Protocol, Network Protocol, or DSP design