RTL Design Engineer Wireless SoC

RTL Design Engineer Wireless SoC (Remote PST)Location: Remote (must be aligned with PST time zone / willing to work PST hours) Rate: DOE We are seeking an experienced RTL Design Engineer to work on next-generation wireless SoC development. The ideal candidate will design and implement high-performance digital blocks and work closely with architecture, analog/mixed-signal, and verification teams to deliver production-quality silicon. Required Skills5+ years of hands-on RTL design experience (S

5+ years of hands-on RTL design experience (SystemVerilog / Verilog)Strong understanding of micro-architecture and RTL implementation from specsExperience in DSP hardware implementation (filtering, FFT, etc.)Knowledge of SoC design flows: CDC, power domains, timing constraints, formal verificationExperience with synthesis, linting, simulation, and STA toolsUnderstanding of DFT concepts (scan, BIST)Strong debugging and problem-solving skillsGood communication and ability to work in cross-function

Title: ASIC/SoC RTL Design Engineer Location: Palo Alto, CA (Or potentially Burlington, MA) Length of Contract: 6 months+ (Temp-to-Perm) Ideal Start: 6/1/2026 Responsibilities : Own end-to-end design of complex SoC subsystems, driving architecture, RTL implementation, and tapeout. Focus on high-performance Datapath, PPA optimization, and cross-functional integration across silicon, firmware, and system teams. Must haves: 8 12+ years in ASIC/SoC digital design with hands-on RTL ownershipStrong Sy

In-Person Interview Required! SoC RTL Design Engineer San Jose, CA: 100% Onsite 6 + Months $60-$62.50/HR Role: Design and develop advanced SoCs across architecture, RTL, and verification. Responsibilities: RTL design, verification, and debugging Support synthesis and timing closure Work with ARM cores, DDR, PCIe, Ethernet, and IP Collaborate with design and bring-up teams Qualifications: Experience in ASIC/SoC design and RTL coding Knowledge of ARM and standard I/O interfaces Dexian stands a