Immediate need for a talented ASIC Verification Engineer (UVM & GLS Focus). This is a 06+months contract opportunity with long-term potential and is located in U.S (Remote). Please review the job description below and contact me ASAP if you are interested.
Job ID:26-32052
Pay Range: $60 -$70/hour. Employee benefits include, but are not limited to, health insurance (medical, dental, vision), 401(k) plan, and paid sick leave (depending on work location).
Key Responsibilities:
- Own verification of complex ASIC/SoC design blocks from planning through sign-off.
- Develop and maintain UVM-based verification environments from scratch, including testbench infrastructure, agents, drivers, monitors, scoreboards, sequences, and coverage models.
- Drive functional verification using directed and constrained-random methodologies and achieve coverage closure.
- Execute and debug Gate-Level Simulations (GLS), including timing-related failures, SDF-annotated simulations, reset issues, X-propagation, and initialization/debug challenges.
- Perform deep waveform analysis, root-cause debugging, regression triage, and verification sign-off activities.
- Collaborate with design, architecture, and customer teams to ensure comprehensive verification coverage and quality.
Key Requirements and Technology Experience:
- 6-10+ years of ASIC/SoC Verification experience.
- Proven experience building complete UVM verification environments from scratch.
- Strong hands-on expertise in:
- SystemVerilog
- UVM
- Gate-Level Simulation (GLS)
- Functional Coverage
- Assertions
- Regression Debugging
- Experience with industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Siemens Questa.
- Strong debugging skills involving waveform analysis, protocol debugging, and root-cause identification.
Our client is a leading IT Industry, and we are currently interviewing to fill this and other similar contract positions. If you are interested in this position, please apply online for immediate consideration.
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