Validation Engineer/ Post-Silicon Engineer/ Design Verification Engineer

Job Role: Validation Engineer/ Post-Silicon Engineer/ Design Verification Engineer

Location: Colorado Springs, CO ( Day One Onsite)

Duration: 6-12 Months

Education: Bachelor s or Master s degree (B.E./B.Tech/MS) in Electronics, Electrical, or Computer Engineering

Role Summary:

We are seeking a highly motivated PCIe Gen6/Gen7 Functional Post-Silicon Validation Engineer to lead the validation of our next-generation PCIe Switch and Retimer silicon. This specialist role focuses exclusively on the functional and protocol-level validation of Gen6 and Gen7 devices. You will be responsible for ensuring robust specification compliance by verifying LTSSM behavior, link training, equalization flows, configuration space, and advanced error handling. This position requires close collaboration with Architecture, Design, and Firmware teams to deliver industry-leading silicon solutions.

Key Responsibilities:

• Silicon Bring-up: Lead the post-silicon bring-up and functional validation of PCIe Gen6/Gen7 Switch and Retimer devices.
• Test Plan Development: Design and execute comprehensive functional validation test plans covering LTSSM state transitions and link initialization.
• Protocol Validation: Validate equalization protocols (including Gen6/Gen7 PAM4 flows), configuration space, and capability structures.
• Data Path & Traffic: Verify flow control, credit management, and data path integrity across posted, non-posted, and completion packets.
• Error & Power Management: Validate error handling (AER, ECRC, NAK/Replay, timeouts) and power management states (ASPM, L1 substates).
• Switch Architecture: Test multi-port and multi-host configurations specifically for Switch devices.
• Advanced Feature Validation: Verify Gen6/Gen7 architectural innovations including FLIT mode operation, PAM4 functional behavior, FEC (Forward Error Correction), and enhanced error containment.
• Interoperability: Conduct rigorous interoperability testing with diverse PCIe ecosystem devices.
• Advanced Debugging: Root-cause functional issues using PCIe protocol analyzers, register-level debugging, trace buffers, and internal debug hooks.
• Automation: Develop Python-based automation frameworks and regression suites to streamline validation cycles.
• Issue Resolution: Drive silicon fixes by collaborating with RTL and firmware teams while documenting test results and coverage.

Required Qualifications:

• PCIe Expertise: Deep understanding of PCIe architecture; Gen5 experience is required, with Gen6 preferred and Gen7 a plus.
• Hands-on Debugging: Proven track record debugging LTSSM failures, link training issues, enumeration problems, and transaction layer/data path bugs.
• Device Experience: Specific experience in the validation of PCIe Switches or Retimers.
• Protocol Knowledge: Strong command of TLP/DLLP structures, flow control, replay buffers, credit logic, and configuration registers.
• Automation: Professional experience in validation automation using Python.

Preferred Qualifications:

• Advanced Technology: Experience with FLIT mode and PAM4-based architectures (Gen6/Gen7).
• CXL Knowledge: Familiarity with the CXL protocol, particularly over PCIe Gen6.
• Platform Exposure: Experience in server platform validation and exposure to emulation or pre-silicon verification environments.
• Compliance: Experience managing interoperability events or functional-focused compliance workshops.

Keywords: PCIe, Gen5, CXL, PAM4, Retimers