Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient GPU! You'll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you'll be crafting and building the technology that fuels Apple's devices. Together, we enable our customers to do all the things they love with their devices. As a member of GPU FE Design integration team, you will create GPU RTL by integrating various IPs following architectural parameters, physical constraints, DFT logic and power intent.
As a GPU Design Integration Engineer, you will be responsible for:\n\n- RTL integration, assembly, partitioning, transformation and analysis.\n- Package, qualify and deliver FE design collateral.\n- Debug simulation failures and triage logic equivalence failures between designs.\n- Ensure implementation readiness with RTL lint, custom checks, unit level synthesis and clock/reset/power domain crossing checks.\n- Develop innovative methods to improve front-end design integration process.\n- Author design integration specification documents.\n- Review and signoff specifications for customers and IP providers.\n- Collaborate effectively with Architecture, IP, DV, SOC, DFT, and IMPL teams spanning multiple sites.
BS + 10 years of experience.\nExperience with Verilog/System Verilog.\nExperience with the one of the following scripting languages: Perl/Ruby/Python.
Proficiency in logic design principles.\nAbility to analyze architectural and micro architectural details to drive design partitioning.\nKnowledge of PPA optimization techniques, Power Intent (UPF/CPF), CDC, RDC, synthesis, physical design and STA.\nExperience with RTL analysis and/or PPA optimization using Invio, LEC and Genus.\nFamiliarity with GPU/CPU/SIMD Architecture and micro-architecture.\nAbility to work well in a team and be productive under aggressive schedules.\nExperience with scalable designs, design reuse, DFT insertion, LEC, Lint, codeline management, simulation and debugging tools.\nAbility to debug and solve various design integration issues in a timely manner.\nAbility to solve complex problems across multiple technical domains.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
- Dice Id: 90733111
- Position Id: 6ff9bb9d99a165cfacf48962d6c28f80
- Posted 1 day ago
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