Analog Layout Design Engineer

Cupertino, CA, US • Posted 11 hours ago • Updated 11 hours ago
Contract Independent
Contract W2
6 Months
No Travel Required
On-site
Depends on Experience
Fitment

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Job Details

Skills

  • Analog Layout
  • CMOS FinFET
  • EDA tools
  • CMOS Drivers
  • High-Speed Data Converters
  • PLLs

Summary

Analog Layout Design Engineer

We are currently looking for an Analog Layout Design Engineer for an onsite position in California with one of our clients. Based on your background, I wanted to reach out regarding this opportunity.

Key Requirements:

  • Minimum 6+ years of experience in Analog Layout Design.
  • Experience developing and leading complex IC layouts for high-speed applications in advanced CMOS FinFET technologies (7nm and below) at both block and chip levels.
  • Thorough knowledge of industry-standard EDA tools such as Cadence, Mentor, and Synopsys.
  • Experience with layout of high-performance analog mixed-signal blocks, including Transceivers, CMOS Drivers, High-Speed Data Converters, and PLLs.
  • Expertise in floor planning, block-level routing, and top-level chip assembly.
  • Knowledge of advanced layout techniques, including floor planning, layer generation, thermal-aware layout design, and electro-migration considerations.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 91095471
  • Position Id: 9015074
  • Posted 11 hours ago
Contact the job poster
John Sunder Singh

John Sunder Singh

IT Recruiter @ Apton Inc
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