VLSI Design Verification Engineer In San Jose, CA
San Jose, CA, US • Posted 7 hours ago • Updated 7 hours agoContract W2
On-site
Depends on Experience


Innovise IT LLC
Fitment
Dice Job Match Score™
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Job Details
Skills
- VLSI
- Forward Error Correction (FEC)
- Ethernet protocols
Summary
Role: Senior/Staff VLSI Engineer Ethernet FEC DV
Duration: 12+ Months
Location: San Jose, CA || Onsite Role
Job Description-:
We are seeking a highly skilled and motivated VLSI Design Verification Engineer with deep expertise in Forward Error Correction (FEC) and Ethernet protocols. In this role, you will own the verification of advanced FEC IP cores (RS-FEC, KR/KP4, or next-gen) within high-speed Ethernet controllers (25G/50G/100G/200G/400G+). You will develop sophisticated UVM environments, define test strategies for complex error-correction scenarios, and drive the verification closure for leading-edge networking silicon
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
- Dice Id: 91159582
- Position Id: 8898721
- Posted 7 hours ago
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