Senior RTL Design Engineer
Contract W2
11 Months
No Travel Required
On-site
$60 - $65/hr
Fitment
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Job Details
Skills
- Design
- develop
- and implement RTL solutions for complex digital and SoC designs. Analyze design specifications and translate them into high-quality RTL implementations. Perform synthesis
- timing analysis
- and design optimization to meet performance
- power
- and area goals. Conduct Clock Domain Crossing (CDC) analysis and Static Timing Analysis (STA) to ensure robust and reliable designs. Work with AMBA AXI-based interconnects and Network-on-Chip (NoC) architectures. Collaborate with verification
- physical design
- and system teams throughout the development cycle.
Summary
Job Title: Senior RTL Design Engineer
Location: Austin, TX (Onsite)
Visa- Any Visa will work
Interview : Virtual Interview/In person
Key Responsibilities
- Design, develop, and implement RTL solutions for complex digital and SoC designs.
- Analyze design specifications and translate them into high-quality RTL implementations.
- Perform synthesis, timing analysis, and design optimization to meet performance, power, and area goals.
- Conduct Clock Domain Crossing (CDC) analysis and Static Timing Analysis (STA) to ensure robust and reliable designs.
- Work with AMBA AXI-based interconnects and Network-on-Chip (NoC) architectures.
- Collaborate with verification, physical design, and system teams throughout the development cycle.
- Debug and resolve RTL, synthesis, timing, and integration issues.
- Interface directly with customers to understand requirements, provide technical guidance, and address design challenges.
- Ensure customer satisfaction through effective communication and timely delivery of project milestones.
- Prepare and present daily and weekly progress reports to customers and internal stakeholders.
- Support project planning, risk assessment, and technical reviews.
Required Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
- 8–10+ years of overall experience in ASIC/SoC Digital Design and RTL development.
- Minimum 5+ years of hands-on experience in Verilog RTL design and development.
- Strong understanding of digital design fundamentals, RTL design methodologies, and synthesis flows.
- Proven experience with EDA tools for:
- Clock Domain Crossing (CDC) analysis
- Static Timing Analysis (STA)
- Logic synthesis
- Strong knowledge of AMBA AXI protocols and related system architectures.
- Experience working with Network-on-Chip (NoC) design and integration.
- Excellent debugging, analytical, and problem-solving skills.
- Strong written and verbal communication skills with the ability to interact directly with customers.
Preferred Qualifications
- Experience working in customer-facing engineering roles.
- Familiarity with complete ASIC/SoC development flows.
- Ability to work independently and manage multiple priorities in a fast-paced environment.
- Experience collaborating with globally distributed teams.
Interested Candidates please share resume on (dot) com
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
- Dice Id: 91173945
- Position Id: 8999942
- Posted 9 hours ago
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