Senior CDC Manager

Hello, Greetings from Clifyx. Position 3: ASIC Engineering Technical Leader Leadthe CDC/RDC (Clock Domain Crossing / Reset Domain Crossing) methodology in silicon one chips Design & implement robust and reusable RTL with CDC/RDC considerations Spec comprehensive CDC/RDC check flows and work with CAD team to implement Review and approve CDC/RDC constraints and waivers Perform static glitch analysis Improve design with prevention of static glitch harzad Bachelor''s or Master''s degree on Ele

Job Title: ASIC Engineering Technical LeaderLocation: RemoteDuration: 12+ month ContractJOB DESCRIPTION:Lead the CDC/RDC (Clock Domain Crossing / Reset Domain Crossing)methodology in silicon one chips Design & implement robust and reusable RTL with CDC/RDC considerations Spec comprehensive CDC/RDC check flows and work with CAD team to implement Review and approve CDC/RDC constraints and waivers Perform static glitch analysisImprove design with prevention of static glitch harzad Bachelor''s or Ma

Title - Lead ASIC DFT Engineer Location Remote (must be aligned with PST time zone) Job Description Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation,

Title - Lead ASIC DFT Engineer Location Remote (must be aligned with PST time zone) Job Description Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation,