Job Title: ASIC/RTL Design Engineer 2
Location: San Jose, CA
Type: 12+ Months Contract
Job Duties:
· The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and AMD internal IP?s.
· Successful candidates will be responsible for leading, and participating in, the design of leading edge SoC?s in advanced digital CMOS processes.
· Our RTL Design Engineers are expected contribute in all aspects of SoC design including Chip
· Definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing closure, Interfacing with physical execution, software, and silicon bring-up teams.
Experience And Education:
· SoC Architecture; knowledge and hand-on experience from industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure.
· Working knowledge of ARM cores and other I/O standard interfaces. An ideal candidate would also exhibit: Strong communication and documentation skills, Good organizational, time management and multitasking skills, Strong initiative and discipline to follow-through, technical leadership
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