FPGA
Logic Designer High-Speed SerDes (Hardware Focus)
Bay Area,
California (On-site/Hybrid)
Long-Term
Contract
Role
Overview
We are
seeking a highly experienced FPGA Logic Designer with deep expertise in high-speed
SerDes architectures and PCIe-based designs. This role focuses on hands-on FPGA
development, integration of transceivers, and implementing complex high-speed
communication protocols in cutting-edge systems.
Core
Technical Requirements
10+ years of FPGA design experience using Xilinx (GTY/GTM)
or Intel (E-Tile/P-Tile/F-Tile) transceivers
Strong expertise in PCIe protocol (Gen4/Gen5/Gen6) design
and implementation
Proven experience working with PCIe on FPGAs (end-to-end
integration)
Deep understanding of high-speed SerDes architectures and signal
integrity challenges
Strong background in MAC / PCS / PMA layers
Expert-level proficiency in Verilog/SystemVerilog RTL design Experience with timing closure in high-frequency FPGA designs
Key
Responsibilities
Design and implement FPGA-based logic for high-speed communication
systems
Develop and optimize PCIe interfaces on FPGA platforms
Integrate and configure high-speed transceivers (GTY/GTM / E-Tile,
etc.)
Perform timing closure, debugging, and hardware validation
Optimize MAC/PCS layers for low latency and high throughput
Collaborate with system architects and board designers
Preferred
Qualifications
Experience with UCIe, CXL, or high-speed Ethernet (400G/800G) Exposure to lab bring-up, debugging tools, and signal analysis
Background working in companies like **Cadence Design Systems,
Siemens, Intel, or Marvell Technology
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