PCIe validation Engineer

Key Responsibilities

Pre-Silicon

• Develop and execute test plans for PCIe Gen3/Gen4/Gen5/Gen6 IP blocks and SoC-level integration
• Create directed and constrained-random tests targeting PCIe Transaction Layer (TLP), Data Link Layer (DLLP), and Physical Layer (PHY) functionality
• Perform protocol-level analysis using VIP (Verification IP) environments and bus functional models
• Debug RTL-level issues related to link training, power management (ASPM, L-states), equalization, and error handling
• Collaborate with design teams on coverage closure, assertions, and functional coverage models

Post-Silicon

• Bring up and validate PCIe links on silicon platforms (FPGA, emulation, and first silicon)
• Develop and execute post-silicon validation test plans covering link training, enumeration, data integrity, error injection, and compliance
• Debug silicon-level issues using protocol analyzers (e.g., Keysight, Teledyne LeCroy), oscilloscopes, and logic analyzers
• Perform root-cause analysis of PCIe link failures, packet errors, and performance degradation
• Characterize PCIe PHY performance including jitter, eye diagrams, and signal integrity
• Collaborate with platform, firmware, and BIOS teams to resolve system-level PCIe issues
• Drive compliance and interoperability testing per PCI-SIG specifications