Photonic Integrated Circuit (PIC) Design & Analysis Engineer

Optical Engineer, Photonic Integrated Circuit (PIC) Design & Analysis

We are seeking a passionate Optical Engineer to join our research and development team. This role focuses on delivering state-of-the-art near-to-eye display system technologies. The ideal candidate will have expertise in novel integrated photonics device design and metrology, gained through a Ph.D. or industry experience.

Responsibilities

• Design and develop complete Photonic Integrated Circuits (PICs), from fundamental component blocks to full-circuit implementations, with a strong emphasis on active device integration.
• Generate, verify, and prepare fabrication-ready layout files, ensuring compliance with foundry Process Design Kits (PDKs) for external fabrication.
• Conduct systematic design analysis, including optimization and parametric studies, to guide design decisions.
• Support the entire design-to-fabrication pipeline, from initial concept through tape-out, coordinating closely with cross-functional teams and external partners.
• Collaborate with program leadership, Technical Program Managers (TPMs), and researchers on PIC designs that align with overall program objectives.

Required Years of Experience: 5-7 years

Minimum Qualifications

• MS or Ph.D. degree in Electrical Engineering, Optical Sciences, Physics, or a closely related field.
• PIC Design & Simulation: 3+ years of hands-on experience in the design, simulation, and layout of photonic integrated circuits (PICs) for visible or IR wavelengths on platforms such as Si, SiN, LiNbO, or BTO.
• Photonic Modeling Tools: 3+ years of experience utilizing photonic device simulation and electromagnetic modeling tools for both device/component and circuit-level analysis (e.g., Lumerical FDTD/MODE/DEVICE, Ansys Photonics, Synopsys RSoft, or COMSOL Multiphysics).
• PIC Layout & Tapeout: 2+ years of experience with PIC layout tools (e.g., KLayout, Cadence Virtuoso, gdsfactory, or equivalent) and GDSII generation, including familiarity supporting tapeouts at commercial foundries with foundry PDK integration and design rule verification.
• 2+ years of experience with scientific programming (e.g., Python or MATLAB) for scripting, design automation, and analysis.
• 1+ years of experience supporting or executing PIC tapeouts at a commercial semiconductor foundry, including an understanding of fabrication process constraints (e.g., propagation losses, sidewall roughness, etch non-idealities).

Preferred Qualifications

• Active PIC Design & Validation: 3+ years experience in active PIC design, fabrication, and validation, particularly for visible wavelengths on LiNbO or BTO platforms.
• Device Characterization: Skills in optical/electro-optic measurements, fiber optics, free-space optics, and PIC packaging.
• Statistical Modeling & Sensitivity Analysis: Experience in design space exploration, yield modeling, and incorporating fabrication constraints.
• 3+ years of experience in design space exploration, sensitivity analysis, and statistical performance/yield modeling for photonic circuits.
• 3+ years of experience with one or more major photonic simulation tool suites (e.g., Lumerical, Synopsys, COMSOL, or equivalent).
• 2+ years of experience utilizing photonic circuit-level simulation tools (e.g., Lumerical Interconnect, Synopsys OptSim, or VPIphotonics) for system-level performance evaluation.
• 2+ years of experience in photonic device characterization and test, including both optical and electro-optic measurements.
• 1+ years experience with fiber optics, free-space optics, PIC packaging, and comprehensive device characterization.
• 1+ years experience with semiconductor fabrication processes and a deep understanding of process-induced performance limitations, such as optical losses, sidewall roughness, and process variability.
• Demonstrated ability to directly incorporate fabrication constraints into PIC designs (e.g., optimizing minimum feature sizes and bend radii, implementing effective tapering strategies, and using layout techniques to mitigate scattering and coupling losses).

Project that team is working on / Products are they supporting

• Developing advanced photonic integrated circuits for next-gen near-to-eye display systems.
• Integrating active devices and optimizing for fabrication constraints.
• Improving system-level performance and yield through design analysis and modeling.

How will progress be evaluated?

• Successful design and tape-out of PICs.
• Quality and innovation in device simulation, layout, and fabrication.
• Effective collaboration and alignment with program goals.
• Ability to optimize designs for performance and manufacturability.

Interview:

• Format: 1 round, panel interview with 2 3 interviewers
• Duration: 1 hour
• Focus: Q&A covering diffractive optics, hands-on experimental experience, and discussion of the candidate s PhD work