Systems Design Engineer - Emulation and Prototyping - Hybrid

Title:                  Systems Design Engineer - Emulation and Prototyping - Hybrid

Mandatory skills:

hardware design, FPGA Design,
Synopsys HAPS, Zebu, Protium, Palladium, FPGA, emulation platforms,
RTL Design, Verilog, System Verilog,
Emulation Platform, Prototyping Platform,
SoC designs, RTL coding, AXI, ACE, APB, PCIe, DDR, Ethernet, SerDes links,
debugging tools, RTL, Verdi, fsdb analysis,
ASIC design flows, emulation, scripting, automation, Python, Perl, Tcl, Make, CMake, Shell,
RTL patches, model creation, production phases, SOC programs

Description:

We are looking for someone with close to 3-5 years of experience in hardware design.
We are looking for to fill as Emulation and Prototyping Engineer. Key skill would be hands on experience with Synopsys HAPS, Zebu, Protium, Palladium, or other FPGA/emulation platforms.

Must have skills:
 FPGA Design Experience
 RTL Design using Verilog/System Verilog
 Exposure to any Emulation or Prototyping Platform (HAPS/Zebu, Protium/Palladium)

JOB DUTIES:
In this position, the engineer will have the following key responsibilities: Hardware emulation model creation. Importing design RTL. Provide RTL patches to address non-synthesis issues. Compile emulation model. Debugging issues found during the process, bring-up, validation, and production phases of SOC programs. Perform pre-silicon verification & validation and emulation to ensure functional correctness and performance. Partition large SoC RTL for multi-FPGA platforms; develop and maintain HAPS/FPGA build infrastructure including scripts, flows, and makefiles. Integrate custom transactors, high-speed interfaces, and debug instrumentation. Work with various pre-silicon tools and concepts such as emulation, FPGA, software models, N-1 silicon usage, etc., including pre-to-post-silicon initiatives

EXPERIENCE AND EDUCATION:
3-4 years of experience on emulation based functional and performance verification for multimillion gate SoC designs. Should have strong exposure to RTL coding and SOC bring-up. Hands-on experience with Synopsys HAPS, Protium, Palladium, or other FPGA/emulation platforms. Experience with SoC buses and protocols: AXI, ACE, APB, PCIe, DDR, Ethernet, SerDes-based links, etc. Strong RTL design background using SystemVerilog/Verilog. Good debugging skills, experience of working with various debugging tools on RTL like Verdi, fsdb analysis. Familiarity with ASIC design flows including emulation, verification and bring up. Expertise in scripting/automation: Python, Perl, Tcl, Make/CMake, Shell.

Notes:
Hybrid Work Environment (As of now), 3 days in Office (Tue, Wed, Thu)

VIVA USA is an equal opportunity employer and is committed to maintaining a professional working environment that is free from discrimination and unlawful harassment. The Management, contractors, and staff of VIVA USA shall respect others without regard to race, sex, religion, age, color, creed, national or ethnic origin, physical, mental or sensory disability, marital status, sexual orientation, or status as a Vietnam-era, recently separated veteran, Active war time or campaign badge veteran, Armed forces service medal veteran, or disabled veteran. Please contact us at for any complaints, comments and suggestions.

Contact Details :

Account co-ordinator: Godwin D Antony Raj, Phone No: , Email id:

VIVA USA INC.
3601 Algonquin Road, Suite 425
Rolling Meadows, IL 60008
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