Austin, Texas
•
Today
Experience with large-scale SoC or AI-class designs At least 5 years of PD experience Hands-on experience at advanced / cutting-edge technology nodes (e.g., N5, N3 or below) Strong understanding of timing closure and correlation between synthesis and implementation Hands-on experience with Cadence Genus and Innovus Ability to work cross-functionally with RTL, architecture, PD, and external implementation teams
Easy Apply
Third Party, Contract
Depends on Experience
