jobs in cupertino, ca, us

Cupertino, California

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Today

The Tier 2 Simulation Infra Support Engineer provides technical support for Mechanical Simulation tools (ANSA/META, Abaqus, Ansys, etc.) The role focuses on strong expertise in the complete simulation workflow, from CAD model preparation to CAE analysis and result interpretation. The role involves developing and executing simulation models, performing finite element analysis (FEA), automating simulation workflows, and working closely with product design and engineering teams to improve product p

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Contract

Depends on Experience

physical design engineer

Mountain View, California

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Today

We are looking for a Physical Design Engineer with hands-on experience in TSMC 3nm/2nm at SOC for cutting-edge GPU / High-Performance designs. Key Responsibilities: 1. Own Netlist-to-GDSII for high-speed, low-power SOC 2. Floorplanning, Placement, CTS, Routing, Timing closure 3. Drive PPA optimization - Power, Performance, Area for 2nm/3nm 4. Handle advanced nodes issues: IR Drop, EM, Crosstalk etc 5. Hands on experience on tools - Synopsys Fusion Compiler, Innovus, Primetime, Calibre Very Imp S

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Contract

Depends on Experience

Physical Design Engineer

Mountain View, California

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Today

Job Title: Physical Design Engineer Location: Mountain View, CA (Onsite) Experience: 5 -10 years in Physical Design Mandatory Skill: Innovous, 2nm, 3nm, 4nm, 5nm Job Description: Key Responsibilities: 1. Own Netlist-to-GDSII for high-speed, low-power SOC 2. Floorplanning, Placement, CTS, Routing, Timing closure 3. Drive PPA optimization - Power, Performance, Area for 2nm/3nm 4. Handle advanced nodes issues: IR Drop, EM, Crosstalk etc 5. Hands on experience on tools - Synopsys Fusion Compiler, In

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Contract

$60 - $70

Physical Design Engineer

Mountain View, California

•

Yesterday

Job Title: Physical Design Engineer Location: Mountain View, CA (Onsite) We are looking for a Physical Design Engineer with hands-on experience in TSMC 3nm/2nm at SOC for cutting-edge GPU / High-Performance designs. Key Responsibilities: 1. Own Netlist-to-GDSII for high-speed, low-power SOC 2. Floorplanning, Placement, CTS, Routing, Timing closure 3. Drive PPA optimization - Power, Performance, Area for 2nm/3nm 4. Handle advanced nodes issues: IR Drop, EM, Crosstalk etc 5. Hands on experience on

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Third Party, Contract

$60+

Physical Design Engineer

Mountain View, California

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11d ago

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Contract

$60 - $70

Physical Design Engineer - W2 Position

Palo Alto, California

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Today

Position : Physical Design Engineer Location : Palo Alto, CA Number of Positions : 5 JD for PD: Exposure to TSMC 2NP/3NP is mustPerform endtoend physical design flow:FloorplanningPower planning (PG grid, IR)Placement & optimizationCTS (Clock Tree Synthesis)RoutingPostroute optimizationAchieve timing closure across all modes and cornersResolve DRC, LVS, ERC and signoff violationsHandle lowpower design techniques:MultiVt, Multivoltage (UPF)Power gating, clock gatingPerform physical verification an

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Contract

$90 - $100

SoC Verification - W2 Position

Remote

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Today

Position : SoC verification Location : Remote is fine Number of Positions : 10 Must Requirement : End-to-end UVM experience from scratch (across test bench infra development, debug, scoreboard etc.) Protocol experience like Ethernet, UCIe, PCIe is a plus but it is not mandatory like the end-to-end UVM expertise. Key Responsibilities Block-Level Verification Ownership: Take full technical ownership of verifying 4-5 complex design blocks per project, ensuring high-quality verification sign-off.Tes

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Contract

$60 - $70

Pega Developer - W2 Position

Remote

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Today

Position: Pega Senior Technical Lead-Remote Remote is ok. JDMust Have8 10 years experience in PRPC developmentExperience upgrading Pega from 8.X to PEGA Infinity 26Certified Pega CSA or CSSA (2019 and before)Experience in eligibility and enrolment systems (e.g., Medicaid, ACA marketplace, CHIP or government benefit programs)Strong hands on in Pega Case management, File Listener, Job Scheduler, Activities, Data Transforms, Flows and UI (Section, harness, Skin) RulesImplement workflows and case m

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Contract

$45 - $50

SoC verification Engineer

Remote

•

Today

Job Title: SoC verification Engineer Location: Remote Job Summary: Must Requirement: End-to-end UVM experience from scratch (across test bench infra development, debug, scoreboard etc.) Protocol experience like Ethernet, UCIe, PCIe is a plus but it is not mandatory like the end-to-end UVM expertise. Key Responsibilities: Block-Level Verification Ownership: Take full technical ownership of verifying 4-5 complex design blocks per project, ensuring high-quality verification sign-off. Testbench & Co

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Contract

$60 - $70

SoC verification Engineer

Remote

•

Yesterday

Position : SoC verification Engineer Location : Remote Must Requirement : End-to-end UVM experience from scratch (across test bench infra development, debug, scoreboard etc.) Protocol experience like Ethernet, UCIe, PCIe is a plus but it is not mandatory like the end-to-end UVM expertise. Key Responsibilities Block-Level Verification Ownership: Take full technical ownership of verifying 4-5 complex design blocks per project, ensuring high-quality verification sign-off.Testbench & Component Devel

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Contract

$70+

jobs in Cupertino, CA, USA