jobs in sunnyvale, ca, us

Sunnyvale, California

•

2d ago

Total Headcount 1 Job Description Core Skills 1. Understanding of Synopsys powerflows (PTPX + PRRTL) 2. Some PD background or understanding of netlist, UPF, SPEF 3. Scripting knowledge Python (required) + tcl. Excel/Gsheet (nice to have) 4. Poweroptimization experience or understanding design+uArch for NoC+Clocking 5. Some background on CTS Second set of skills 1.Understanding of powerfundamentals and experience with Synopsys powerestimation tools (PrimePower, PPRTL). 2.Familiarity with

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Full-time

200000

Hardware Program Manager (Only W2)

Santa Clara, California

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5d ago

JD: We need someone with Hardware; electricals background and with experience in handling a team size of 30 to 50. Lead a large, cross-functional U.S.-based organization of 3050 engineers and program staff, driving people leadership, strategic customer relationships, and execution of complex hardware programs. You''ll be the bridge between engineering, executive stakeholders, and key customers ensuring organizational health, customer satisfaction, and on-time delivery. What You''ll Be Doing P

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Full-time

140,000 - 150,000

Hardware Validation Engineer (Only W2)

Santa Clara, California

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2d ago

Salary: 100K+ benefitsFulltime onlyLocation- Santa Clara 100% on-siteExp- 3yrs-15yrs Post Silicon Validation Engineering BS Degree in EE with one or two years of experienceKnowledge of board bring up,HW troubleshooting skillsand board testing as per the test planFamiliarity of working in lab environment inelectrical measurements of different IO interfaces(PCIE, USB, HMDI and I2C/SPI)and using Test Equipment like Oscilloscope, DAQ, Multi-meter, Power Supply and Logic analyserAbility to read sche

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Full-time

100000

Physical Design Engineer (PnR / PPA / Timing Closure) (Only W2))

Mountain View, California

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4d ago

Job Description We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification. Optimize designs for Power, Performance, and Area (PPA) targets. Achieve timing closure

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Full-time

140,000 - 150,000

Post Silicon Validation (Only W2)

Sunnyvale, California

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4d ago

Engineer does not need to have ML-coprocessor background. Display domain is more important. Validate display SOC, Mixed Signal SOC, and IP. (good) Define validation strategy and test plans for new IP blocks, aligning with RTL, architecture, FW. (good) Develop silicon validation infrastructure and coding C/C++ and Python for emulation (Zebu), FPGA (HAPS), and first silicon platforms. Identify risks and develop mitigation strategies. (Good) Execute bring-up/debug, workload enablement, and SW stack

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Full-time

120,000 - 140,000

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jobs in Sunnyvale, CA, USA