2.5D Jobs in California

1 - 16 of 16 Jobs

CoWoS Principle Packaging EngineerJob Title - CoWoS Principle Packaging Engineer

Zachary Piper Solutions, LLCCompany Name - Zachary Piper Solutions, LLC

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Saratoga, California, USA

Full-time

Piper Companies is looking for a CoWoS Principle Packaging Engineer who will construct and enhance Chip-on-Wafer-on-Substrate packaging technology to support high-performance AI and data center applications onsite in Saratoga, CA . The ideal CoWoS Principle Packaging Engineer will collaborate with cross-functional teams to facilitate smooth integration of advanced multi-die packages. Responsibilities for the CoWoS Principle Packaging Engineer: Lead the advancement of CoWoS packaging technolog

Director of Packaging Engineering - CoWoSJob Title - Director of Packaging Engineering - CoWoS

Zachary Piper Solutions, LLCCompany Name - Zachary Piper Solutions, LLC

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Saratoga, California, USA

Full-time

Piper Companies is seeking a Director of Packaging Engineering - CoWoS to join our dynamic team onsite 5 days per week in Saratoga, CA. The Ideal Director of Packaging Engineering - CoWoS will spearhead the development and refinement of Chip-on-Wafer-on-Substrate packaging technology for high-performance AI and data center applications. Responsibilities for the Director of Packaging Engineering - CoWoS Lead the advancement of CoWoS packaging technology to enhance chip performance, power, and

Principal Packaging EngineerJob Title - Principal Packaging Engineer

Zachary Piper Solutions, LLCCompany Name - Zachary Piper Solutions, LLC

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Saratoga, California, USA

Full-time

Piper Companies is seeking a Principal Packaging Engineer who will develop and refine Chip-on-Wafer-on-Substrate technology. The Packaging engineer will be preferred in office in Saratoga, CA, but is open to remote. Requirements for the Packaging Engineer include: - Innovate and enhance CoWoS packaging processes to boost chip performance, power efficiency, and reliability. - Collaborate with design, test, and manufacturing teams to ensure flawless chip-package integration. - Lead failure analys

Senior Chassis Mechanical Design EngineerJob Title - Senior Chassis Mechanical Design Engineer

Zachary Piper Solutions, LLCCompany Name - Zachary Piper Solutions, LLC

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Saratoga, California, USA

Full-time

Piper Companies is currently seeking a Senior Chassis Mechanical Design Engineer to work on-site in Saratoga, CA 5 days per week . The ideal Senior Chassis Mechanical Design Engineer is eager to solve complex challenges and help shape the future of AI networking technologies. Responsibilities of the Senior Chassis Mechanical Design Engineer: Design and optimize chassis components using CAD software (SolidWorks, AutoCAD, CATIA). Develop and improve IC packages, focusing on thermal management, e

Microelectronics Advanced Packaging SMEJob Title - Microelectronics Advanced Packaging SME

Booz Allen HamiltonCompany Name - Booz Allen Hamilton

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Remote

Full-time

Job Number: R0216856 Microelectronics Advanced Packaging SME Key Role: Provide technical leadership and subject matter expertise to U.S. government clients in the areas of advanced microelectronics packaging technologies, including silicon interposer assemblies, flip chip, BGA, advanced interconnect, multi-chip modules, and 2.5D or 3D heterogenous integration. Identify and assess the performance of packaging providers and technologies against defense needs and requirements. Define strategies and

System Signal/Power Integrity EngineerJob Title - System Signal/Power Integrity Engineer

Broadcom CorporationCompany Name - Broadcom Corporation

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San Jose, California, USA

Full-time

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: System Signal/Power Integrity Engineer Responsibilities Support high data rate SerDes applications - up to 112Gbps NRZ and 224G PAM4 systemsSystem level Signal and Power Integrity design trade-offs and debugCollaborate with package, PCB, and silicon d

Signal Integrity Engineer, PrincipalJob Title - Signal Integrity Engineer, Principal

Marvell Semiconductor Inc.Company Name - Marvell Semiconductor Inc.

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Santa Clara, California, USA

Full-time

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and be

Failure Analysis Staff EngineerJob Title - Failure Analysis Staff Engineer

Marvell Semiconductor Inc.Company Name - Marvell Semiconductor Inc.

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Santa Clara, California, USA

Full-time

Sr. Principal Package EngineerJob Title - Sr. Principal Package Engineer

Marvell Semiconductor Inc.Company Name - Marvell Semiconductor Inc.

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Santa Clara, California, USA

Full-time

ASIC Package Signal/Power Integrity EngineerJob Title - ASIC Package Signal/Power Integrity Engineer

Cisco Systems, Inc.Company Name - Cisco Systems, Inc.

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San Jose, California, USA

Full-time

The application window is expected to close on 05/09/2025. The job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team Cisco Silicon One is a business organization with a long track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world's most complex networks and carry over 90% of IP traffic. We are a highly specialized ASIC team with experts in all aspects of advanced IC pack

Package Development, Signal Integrity and Power Integrity Engineer, StaffJob Title - Package Development, Signal Integrity and Power Integrity Engineer, Staff

Marvell Semiconductor Inc.Company Name - Marvell Semiconductor Inc.

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Santa Clara, California, USA

Full-time

Senior Signal and Power Integrity Engineer - HardwareJob Title - Senior Signal and Power Integrity Engineer - Hardware

NVIDIA CorporationCompany Name - NVIDIA Corporation

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Santa Clara, California, USA

Full-time

We are now looking for a Senior Signal & Power Integrity Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and

Chip Desgner/PackagingJob Title - Chip Desgner/Packaging

eTeam, Inc.Company Name - eTeam, Inc.

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Santa Clara, California, USA

Contract

Job Title: Chip Desgner/Packaging Job Location: Santa Clara, CA (Hybrid) IC Packaging & Chiplet Integration : 2.5D/3D packaging, flip-chip bonding, TSV, hybrid bondingSemiconductor Processing : BEOL/FEOL integration, advanced interconnects, thin-film deposition (PVD, PECVD, ALD, CVD)Design & Simulation : Siemens NX, Cadence, ANSYS, EasyEDA, ThermoCalcHigh-Speed I/O & Signal Integrity : Impedance control, power/signal integrity, substrate optimizationProcess Development & Metrology : DOE, SPC,

Semiconductor Engineer in Santa Clara, CAJob Title - Semiconductor Engineer in Santa Clara, CA

Talented ITCompany Name - Talented IT

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Santa Clara, California, USA

Full-time

Job Title: Principal Advanced Packaging Engineer Semiconductor & Chiplet Integration Location: Santa Clara, CA Visas: and H1b Industry: Semiconductor | Microelectronics | Advanced Packaging Experience Level: Senior (10+ Years) Position Summary We are seeking an experienced Principal Advanced Packaging Engineer with deep expertise in semiconductor packaging, chiplet integration, and high-speed interconnect design. This role will lead advanced packaging development efforts for next-generation AI

ASIC Package SI/PI EngineerJob Title - ASIC Package SI/PI Engineer

Datum Software, Inc.Company Name - Datum Software, Inc.

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San Jose, California, USA

Contract, Third Party

Job Description: ASIC Package SI/PI Engineer Location: San Jose, CA 100% Onsite ASIC Package Engineer SI/PI Responsibilities: Drive chip-package-system co-design by driving signal and power integrity requirements analysis and optimizationDefine power tree structure, netlists, etc for High Performance Computing based on 2.5D/3D package technologyRun pre-layout and post-layout simulation flow with a focus on high-speed interface and PDN, create simulation models and develop simulation methodology

PCB Layout EngineerJob Title - PCB Layout Engineer

Randstad DigitalCompany Name - Randstad Digital

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Remote or Phoenix, Arizona, USA

Contract

job summary: Exciting opportunity for an experienced Principal PCB & Substrate Layout Engineer to join a growing, engaging, and collaborative team. As a valued team member, you will collaborate to deliver leading edge microelectronics that are game changing and impactful to our nation's defense. The successful candidate will be part of a dynamic team that is transforming the business and the defense-grade microelectronics industry while executing on near-term program commitments while fosteri