ASIC jobs in Nashua, NH

ASIC Verification Engineer (UVM & GLS Focus)

Remote

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9d ago

Position : ASIC Verification Engineer (UVM & GLS Focus) Location : Remote is fine Number of Positions : 7 Must-Have Skills Strong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock

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Contract

Depends on Experience

Lead ASIC DFT Staff Engineer

Remote

•

Today

Job Description: Key Skills : "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertio

Contract

USD70.0/HOURLY - USD80.0/HOURLY

ASIC DESIGN LEAD / SENIOR CHIP DESIGN ENGINEER

Remote

•

Today

ASIC CHIP LEAD ASIC Design Lead / Senior Chip Design Engineer What Youll Do Architecture and Chip Definition Lead ASIC architecture development from high-level requirements and block diagrams. Work with system architects to define chip functionality, interfaces and performance goals. Write detailed specifications for chip components and subsystems. RTL Design and Synthesis Develop RTL designs and run synthesis with Synopsys Design Compiler. Tune RTL for power, performance and area. Design, imp

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Contract

100+

ASIC Design Lead / Senior Chip Design Engineer

Remote

•

Yesterday

Role:ASIC Design Lead / Senior Chip Design Engineer Location:REMOTE Duration: 12 months Contract Job Description What Youll Do Architecture and Chip Definition Lead ASIC architecture development from high-level requirements and block diagrams. Work with system architects to define chip functionality, interfaces and performance goals. Write detailed specifications for chip components and subsystems. RTL Design and Synthesis Develop RTL designs and run synthesis with Synopsys Design Compiler. Tun

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Contract

95 - 105

ASIC Verification Engineer (UVM & GLS Focus)

Remote

•

2d ago

Must-Have SkillsStrong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock synchronization issues, power-up sequence validation, and debug of post-synthesis/post-layout simulation fa

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Contract

65 - 70

Lead ASIC DFT Staff Engineer

Remote

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8d ago

Required Skills & Qualifications: Strong hands-on experience in ASIC DFT with end-to-end ownership.Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.Experience with MBIST implementation and verific

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Third Party, Contract

90 - 100

ASIC Verification Engineer (UVM & GLS Focus)

Remote

•

9d ago

Job Description: Must-Have Skills Strong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock synchronization issues, power-up sequence validation, and debug of post-synthesis/post-la

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Contract

Depends on Experience

ASIC/FPGA Design Verification Engineer (Teradyne, N. Reading, MA)

Reading, Massachusetts

•

Today

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world! We

Full-time

USD 98,700.00 - 157,900.00 per year

ASIC Verification Engineer (TERADYNE, North Reading, MA)

Reading, Massachusetts

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Today

Full-time

USD 123,100.00 - 196,900.00 per year

ASIC FPGA Engineer

Remote or Boise, Idaho

•

Today

Basic Qualifications Education Requirements: Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 2 years of relevant experience; or Master's degree, plus 6 months of relevant experience. Clearance Requirements: Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility req

Full-time

USD 103,585.00 - 110,000.00 per year

ASIC/FPGA Methodology Engineer (TERADYNE, North Reading, MA)

Reading, Massachusetts

•

Today

Full-time

USD 154,900.00 - 247,800.00 per year

Sr. SOC Engineer

Boxborough, Massachusetts

•

Today

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you're designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Joi

Full-time

USD 156,100.00 per year

FPGA Digital Design Engineer II

Tewksbury, Massachusetts

•

Today

Job DescriptionDate Posted: 2026-09-22\nCountry: United States of America \nLocation: US-MA-TEWKSBURY-TB1 ~ 50 Apple Hill Dr ~ ASSABET BLDG \nPosition Role Type: Onsite \nU.S. Citizen, U.S. Person, or Immigration Status Requirements: The ability to obtain and maintain a U.S. government issued security clearance is required. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance \nSecurity Clearance Type: DoD Clearance: Secret \nSecurity Clearance Status: Ac

Full-time

Senior FPGA Design Engineer

Tewksbury, Massachusetts

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Today

Job DescriptionDate Posted: 2026-08-11\nCountry: United States of America \nLocation: US-MA-TEWKSBURY-TB1 ~ 50 Apple Hill Dr ~ ASSABET BLDG \nPosition Role Type: Onsite \nU.S. Citizen, U.S. Person, or Immigration Status Requirements: The ability to obtain and maintain a U.S. government issued security clearance is required. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance \nSecurity Clearance Type: DoD Clearance: Secret \nSecurity Clearance Status: Ac

Full-time

Senior Embedded Security Engineer - Digital Systems Security

Bedford, Massachusetts

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Today

At MITRE, your passion fuels work that impacts our nation and improves lives. This is where your skills strengthen national security, cybersecurity, health, transportation, and citizen services. We're a nonprofit engineering, applied research, and advanced technology organization working in the public interest. With objectivity and integrity at our core, we lead federally funded research and development centers for U.S. government agencies - collaborating with industry and academia to deliver in

Full-time

USD 126,800.00 - 158,500.00 per year

FPGA Engineer (with Secret Clearance)

Manchester, New Hampshire

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6d ago

Job Title: FPGA Engineer (with Secret Clearance) Location: Manchester, NH Onsite (Other back-up locations to work out of can be Nashua, NH, Totowa, NJ, and Austin, TX) Duration: 12 months- 24 months + possible extension Ideal Start Date: 11/2 or later Work Schedule: 9/80 Active Secret Clearance Required Background Check/Drug Screen Both Required W2 Required Required Skills and Education Junior, Mid-level, and/or Senior level years of relevant experience with bachelor's degree (less years with

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Contract

70 - 100

Lead Firmware Engineer

Woburn, Massachusetts

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Today

System Development Division (SDD) is focused on delivering National Defense capabilities by driving mission-focused strategies to develop advanced technology systems enabling enduring products and solutions focused on achieving the customer vision. Our programs deliver sustainable, reliable, and cost-efficient capabilities focused on end-customer needs that function in operationally relevant environments and timeframes. SDD considers the entire lifecycle of the solution, from conceptualization a

Full-time

USD 173,000.00 - 238,000.00 per year

DFT (Design For Test) Lead - Remote Role

Remote

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Today

Role: ASIC DFT (Design for Test) LeadLocation: RemoteDuration: 12+ months (possibly extending longer based on project timelines)Candidate Responsibilities:Responsible for implementing the Hardware Design-for-Test (DFT) features - scan, mbist, BISR, boundary scan, setting up/debugging DFT simulations and supporting post-silicon testing/debugResponsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with t

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Contract

Depends on Experience

DFT (Design for Test) Lead

Remote

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21d ago

Job Title: DFT (Design for Test) Lead Location: (Remote) Shift: 9am 5pm PST Duration: 12+ Months Contract Role on W2 Job Responsibilities:Responsible for implementing the Hardware Design-for-Test (DFT) features - scan, mbist, BISR, boundary scan, setting up/debugging DFT simulations and supporting post-silicon testing/debugResponsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability f

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Contract

75 - 80

Senior Digital Product Configuration Management Engineer Test Equipment Support

Andover, Massachusetts

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Today

Job DescriptionDate Posted: 2026-09-17\nCountry: United States of America \nLocation: US-MA-ANDOVER-AN1 ~ 350 Lowell St ~ AN1 ESSEX BLDG \nPosition Role Type: Onsite \nU.S. Citizen, U.S. Person, or Immigration Status Requirements: Active and transferable U.S. government issued security clearance is required prior to start date. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance \nSecurity Clearance Type: DoD Clearance: Secret \nSecurity Clearance Status

Full-time

ASIC jobs in Nashua, NH, USA