ASIC jobs in Palo Alto, CA

ASIC/SOC DFT Engineer (Silicon Engineering)

Palo Alto, California

•

Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. ASIC/SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

USD 135,000.00 - 175,000.00 per year

ASIC Design Hardware Engineer - SDC/STA - San Jose, CA (Hybrid)

Hybrid in San Jose, California

•

3d ago

ASIC Design Hardware Engineer - SDC/STA (Hybrid) Location: San Jose, California, United States of America You are a diligent Design / SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will develop timing constrains at both block level and fu

Easy Apply

Third Party, Contract

$70+

ASIC/RTL Design Engineer

San Jose, California

•

10d ago

Job Description: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and internal IPs. Successful candidates will be responsible for leading, and participating in, the design of leading edge SoC?s in advanced digital CMOS processes.Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro

Easy Apply

Third Party, Contract

Depends on Experience

Remote (PST time zone preferred) -- Lead ASIC DFT Engineer

San Jose, California

•

19d ago

Hello Professional, Good Afternoon Please find the job description give below, if interested please share me your most updated copy of resume. Role: Lead ASIC DFT Engineer Work Setup: Remote, PST time zone preferred Experience Required:10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep tec

Easy Apply

Contract, Third Party

Depends on Experience

Sr. ASIC DFT Engineer (Silicon)

Palo Alto, California

•

Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

USD 175,000.00 - 280,000.00 per year

ASIC Emulation Engineer

San Jose, California

•

19d ago

Key Skills:Veloce, Palladium, or ZeBu, PCIe and UCIe and memory technologies such as LPDDR and HBM Set up and maintain Siemens Veloce emulation and prototyping platforms Adapt SoC designs for Emulation and Prototyping Develop and debug emulation testbenches and system-level environments Support pre-silicon validation, power/performance analysis, and early software bring-up. Participate in silicon bring-up and validation. Collaborate with design and verification teams to isolate design issues and

Easy Apply

Contract

60 - 75

ASIC Manufacturing Project Architect

San Jose, California

•

2d ago

Were hiring for a full-time opportunity with a leading semiconductor R&D organization in USA. This role focuses on ASIC Manufacturing Project Architect. Detailed job description is given below. Please share your resume to Job Title: Project Architect Backend (ASIC Manufacturing / Semiconductor) Location:San Jose, CA (Onsite) Type: Full-Time | Direct Hire with End Client Experience:10+ Years Job Summary We are seeking an experienced Project Architect to lead technical customer engagement

Easy Apply

Full-time, Third Party

Depends on Experience

ASIC DFT Staff Engineer

Remote

•

2d ago

Job Title: ASIC DFT Staff Engineer Location: Remote Job Description: Key Skills: "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical own

Easy Apply

Third Party, Contract

Physical Design Engineer

San Jose, California

•

25d ago

Position: Physical Design Engineer Location: San Jose, CA Hybrid Duration: 12 Months VISA: H-1, USC Position Overview We are seeking an experienced Physical Design Engineer to support the implementation of high-performance semiconductor designs targeting advanced process technologies. This contract position will focus on synthesis, floorplanning, physical implementation, and performance optimization for complex, timing-sensitive designs while working closely with cross-functional engineering

Easy Apply

Third Party

$$70-$80 C2C

Technical Leader Network SDK QA | Saratoga, CA

Saratoga, California

•

6d ago

We are seeking a hands-on Technical Leader Network SDK QA to lead the quality strategy for next-generation switching platforms. In this role, you will own SDK validation, design automated test frameworks, mentor QA engineers, and collaborate with SDK, ASIC, and Network OS teams to ensure reliable, high-performance software releases. Required Skills: 8+ years of QA/validation experience in networking SDKs, Network OS, or embedded systemsStrong knowledge of L2/L3 networking, ACLs, QoS, and multica

Easy Apply

Full-time

Depends on Experience

Senior ASIC RTL DESIGN Engineer

Remote or Hybrid in Boston, Massachusetts

•

10d ago

12 Months + CONTRACT Starting in September SKILLS: SENIOR ASIC RTL Design Verilog High Speed Memory Interface Experience Logic synthesis & Timing constraints Forward Error Correction (FEC), Bit Rate Error (BER) calculations Integrating Soft IP from Industry Standard and Custom IP into the design Bandwidth calculation Prefer experience with some of: LPDDR5 UFS/FlashPCIe Gen4/5

Easy Apply

Contract

90 - 130

Lead ASIC DFT Engineer

Remote

•

20d ago

Role: Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 10+ yrs to 15 yrs. Job Description: We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts a

Easy Apply

Third Party, Contract

110 - 120

High-Speed EDA/CAD Engineer (Analog & Mixed Signal)

Sunnyvale, California

•

6d ago

Position:High-Speed EDA/CAD Engineer (Analog & Mixed Signal) Location:Sunnyvale, CA Hybrid 3 days onsite (relocation candidates is fine) Duration:24+ month contract Domain:Analog & Mixed Signal EDA/CAD Job Description: Client is seeking an EDA/CAD Engineer to support and develop SiGe and CMOS design solutions for the high-speed analog ASIC design team. The engineer will be hands-on with all phases of tool flow, including PDK installation and support, tool support and installation, layou

Easy Apply

Contract

$60 - $70

Senior Electrical Engineer

Hybrid in Palo Alto, California

•

2d ago

Senior Electric Engineer Youll own the electrical engineering team for a breakthrough stealth-stage neurotechnology and brain-computer interface (BCI) startup building an AI-powered neural interface platform. In this role, you will own the wearable electrical architecture from schematic through production, helping bring a highly integrated next-generation device to market. The platform combines cameras, spatial audio microphones, EEG sensors, Wi-Fi/BLE connectivity, and advanced power managemen

Easy Apply

Full-time

225000 - 250000

Design Verification Engineer

San Jose, California

•

19d ago

Job Title: Design Verification Engineer Location: San Jose, CA Experience: 8+ Years Type: Contract Description: This requirement is for a Senior Design Verification (DV) Engineer focused on verifying complex semiconductor IPs and SoCs before silicon fabrication. The client is looking for someone who can independently build verification environments, create test plans, and identify design bugs early in the development cycle. Key Skills Required 8+ years of Design Verification experience in s

Easy Apply

Contract

Depends on Experience

ASIC Implementation Engineer STA

San Jose, California

•

Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: The Full Chip Static Timing Analysis (STA) Engineer is responsible for ensuring that ASIC meets its performance targets and timing requirements across all operating conditions. Key Responsibilities: Full-Chip Timing Sign-off: Own the final timing clos

Full-time

USD 143,800.00 - 230,000.00 per year

ASIC Implementation Engineer PD

San Jose, California

•

Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the Asic Products Division. This position involves working with the latest technology to continue driving next generation Artificial Intelligence and PCIe Switch Pro

Full-time

USD 121,900.00 - 195,000.00 per year

Senior Custom ASIC Engineering Lead

San Jose, California

•

Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Are you a versatile, senior engineer capable of leading external and internal cross-functional teams in areas such as physical design, STA, DFT, and packaging? Have you taped out so many chips that you can identify potential design problems hidden in E

Full-time

USD 143,800.00 - 230,000.00 per year

Principal Engineer, ASIC Design

San Jose, California

•

Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are building the next generation of solid-state drive controllers at Micron, where cutting-edge ASIC design meets high-performance storage innovation. Our team works across the full silicon life

Full-time

USD 198,000.00 - 336,000.00 per year

Sr. Staff Engineer, ASIC Design

San Jose, California

•

Today

Sr. Staff Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged o

Full-time

USD 180,000.00 - 223,000.00 per year

ASIC jobs in Palo Alto, CA, USA