ASIC jobs in San Diego, CA

ASIC Verification Engineer (UVM & GLS Focus)

Remote

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9d ago

Position : ASIC Verification Engineer (UVM & GLS Focus) Location : Remote is fine Number of Positions : 7 Must-Have Skills Strong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock

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Contract

Depends on Experience

Lead ASIC DFT Staff Engineer

Remote

•

Today

Job Description: Key Skills : "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertio

Contract

USD70.0/HOURLY - USD80.0/HOURLY

ASIC Power Engineer

Remote

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3d ago

ASIC Power Engineer to perform power analysis and optimizations in ASIC for AR/VR products. Areas of interests includes Machine Learning. Primary languages are Python, TCL, and SystemVerilog (SV). RESPONSIBILITIES - Set up and maintain PPRTL and PTPX power analysis flows (average and time-based/peak power). - Generate and manage activity inputs (FSDB/VCD/SAIF) from RTL and gate-level simulations; handle long-waveform and windowed analysis. - Correlate RTL-level power estimates against gate-leve

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Contract

$100 - $115

ASIC DESIGN LEAD / SENIOR CHIP DESIGN ENGINEER

Remote

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Today

ASIC CHIP LEAD ASIC Design Lead / Senior Chip Design Engineer What Youll Do Architecture and Chip Definition Lead ASIC architecture development from high-level requirements and block diagrams. Work with system architects to define chip functionality, interfaces and performance goals. Write detailed specifications for chip components and subsystems. RTL Design and Synthesis Develop RTL designs and run synthesis with Synopsys Design Compiler. Tune RTL for power, performance and area. Design, imp

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Contract

100+

ASIC Design Lead / Senior Chip Design Engineer

Remote

•

Today

Role:ASIC Design Lead / Senior Chip Design Engineer Location:REMOTE Duration: 12 months Contract Job Description What Youll Do Architecture and Chip Definition Lead ASIC architecture development from high-level requirements and block diagrams. Work with system architects to define chip functionality, interfaces and performance goals. Write detailed specifications for chip components and subsystems. RTL Design and Synthesis Develop RTL designs and run synthesis with Synopsys Design Compiler. Tun

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Contract

95 - 105

ASIC Verification Engineer (UVM & GLS Focus)

Remote

•

2d ago

Must-Have SkillsStrong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock synchronization issues, power-up sequence validation, and debug of post-synthesis/post-layout simulation fa

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Contract

65 - 70

Lead ASIC DFT Staff Engineer

Remote

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8d ago

Required Skills & Qualifications: Strong hands-on experience in ASIC DFT with end-to-end ownership.Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.Experience with MBIST implementation and verific

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Third Party, Contract

90 - 100

ASIC Verification Engineer (UVM & GLS Focus)

Remote

•

9d ago

Job Description: Must-Have Skills Strong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock synchronization issues, power-up sequence validation, and debug of post-synthesis/post-la

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Contract

Depends on Experience

Next-Gen System Cache ASIC Digital Design Engineer

San Diego, California

•

Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (

Full-time

USD 121,800.00 - 182,600.00 per year

AI/ML driven ASIC Design and Implementation Automation Engineer

San Diego, California

•

Today

As an AI/ML driven ASIC Design and Implementation Automation Engineer in our Advanced Chip Engineering (ACE) organization, you will work in a dynamic environment to explore methodology, flows and tools to improve efficiency and quality of results (power, performance, area, and quality) for SoC and IP development teams across the organization. You'll be working and connecting with AI/ML and automation experts in the industry as well as academia to explore state-of-the-art AI/ML CAD techniques as

Full-time

USD 125,000.00 - 171,900.00 per year

Sr Principal AI/ML Driven ASIC Design and Implementation Automation Expert

San Diego, California

•

Today

As an Sr Principal AI/ML driven ASIC Design and Implementation Automation Expert in our Advanced Chip Engineering (ACE) organization, you will work in a dynamic environment to explore methodology, flows and tools to improve efficiency and quality of results (power, performance, area, and quality) for SoC and IP development teams across the organization. You'll be working and connecting with AI/ML and automation experts in the industry as well as academia to explore state-of-the-art AI/ML CAD tec

Full-time

USD 179,800.00 - 247,200.00 per year

AI/ML Driven ASIC Design and Implementation Automation Engineer

San Diego, California

•

Today

Full-time

USD 147,900.00 - 203,400.00 per year

ASIC FPGA Engineer

Remote or Boise, Idaho

•

Today

Basic Qualifications Education Requirements: Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 2 years of relevant experience; or Master's degree, plus 6 months of relevant experience. Clearance Requirements: Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility req

Full-time

USD 103,585.00 - 110,000.00 per year

ASIC DTCO, Timing and Technology Engineer

San Diego, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a DTCO and Timing Engineer, you will play a vital role in DTCO analysis targeting the Mobile, Compute, Automotive and IOT markets The candidate will work with best-in-class methodologies, tools and implementation flows/technologies to evaluate process technology entitlement (PPAY) for SOC products at the block/IP-level and at system-level in advanced process technologie

Full-time

USD 145,600.00 - 218,400.00 per year

Software Development Engineer

San Diego, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: This individual possesses the solid engineering fundamentals and understanding with some supervision in the design, development, integration, testing and validation, and performance optimization of low-level device driver software, firmware and Hardware/Software interfaces for all new MSM ASIC chipsets. Reviews systems specifications, requirements and working parameters

Full-time

USD 134,347.00 - 141,200.00 per year

SOC Power Architect

San Diego, California

•

Today

Full-time

USD 174,400.00 - 261,600.00 per year

Senior SoC Debug Engineer

San Diego, California

•

Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm's Silicon Validation team is part of the central SoC digital hardware organization responsible for the overall quality of the SoC silicon. The validation team works closely with architects, designers, verification engineers, software engineers, and customers. We are currently seeking a candidate for the position of Senior SoC Debug Engineer. In this role, the cand

Full-time

USD 121,800.00 - 182,600.00 per year

Senior Ultrasound Embedded Software Engineer – IVUS

San Diego, California

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29d ago

Business Title: Senior Ultrasound Embedded Software Engineer IVUS Location: San Diego, CA Job Type: Contract Job Overview: We are seeking a Senior Embedded Software Engineer to support the development of a next-generation Intravascular Ultrasound (IVUS) medical device. The ideal candidate will have strong experience in embedded C/C++, hardware/software integration, FPGA/electronics, and data acquisition.Key Responsibilities: Design, develop, integrate, and debug embedded software using C/C++.De

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Contract, Third Party

Depends on Experience

SOC Power Architecture Engineer

San Diego, California

•

Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > Camera Engineering General Summary: Qualcomm provides complete chipset solution that includes CPU, Modem, Application Processor, Multi-media engines, Interconnect and more. Power is a key area that drives the value of our chips. As fabrication technology node shrinks, and performance requirement become higher, it is crucial to provide power optimized solutions, which is the responsibility of the group that y

Full-time

USD 109,400.00 - 164,200.00 per year

Sr. DFT Engineer, Amazon Leo

San Diego, California

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Today

Be part of Amazon LEO?s sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies. In this role you will: Architect and def

Full-time

ASIC jobs in San Diego, CA, USA