DDR SDRAM jobs | Dice.com

Markham, Ontario

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2d ago

We are looking for Systems Engineer 2 for our client in Markham ON Job Title: Systems Engineer 2 Job Location: Markham ON Job Type: Contract Job Overview: Pay Range: $60.51hr - $63.87hr Requirement/Must Have: Thorough understanding of PC industry standard busses, such as HT, PCI, PCIe, LPC, USB, and SATA.Detailed knowledge of high speed digital design and signal integrity.Strong understanding of BIOS, OS and driver interactions at the system level.Proficient understanding of x86 CPU architecture

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Contract, Third Party

Depends on Experience

FPGA layout engineer

Pleasanton, California

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Today

Job#: 3043768 Job Description: FPGA Engineer Location: Pleasanton, CA (Onsite) Role Overview We are seeking a Senior FPGA Layout Engineer for an aerospace and defense team. This role requires an individual who can operate independently to develop secure computing products, processor boards, and box-level solutions. The position focuses on laying out complex FPGA- and processor-based boards with minimal ramp-up time. Key Responsibilities Perform complex board layouts for advanced FPGA-based

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Full-time

$80 - $110 per hour

Air Vehicle Depot Induction Manager

Utah

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Today

Job Number: R0243408 Air Vehicle Depot Induction Manager The Opportunity: As a product support analyst, you know the importance of delivering strategic, data-driven logistics solutions that enable product success and long-term sustainability. On our team, you'll play an essential role in lifecycle logistics to support critical national defense missions. Your contributions will directly impact readiness, planning, and efficiency as you help shape and implement innovative logistics solutions. Thi

Full-time

USD 52,900.00 - 108,000.00 per year

DDR PHY Signal Integrity and Power Integrity Engineer

Santa Clara, California

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2d ago

We are looking for DDR PHY Signal Integrity and Power Integrity Engineer for our client in Santa Clara,CA Job Title: DDR PHY Signal Integrity and Power Integrity Engineer Job Location: Santa Clara,CA Job Type: Contract Job Overview: Pay Range: $71.42hr - $85.71hr Requirement/Must Have: Signal integrity (SI) and power integrity (PI) knowledge, including S-parameter/Z-parameter analysis, channel modeling, and PDN modeling.Knowledge of Ansys or Cadence simulation tools (e.g., HFSS, SIwave, Sigrity,

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Third Party, Contract

Depends on Experience

PCB Design Engineer (Cadence Allegro V17.2/17.4)

Austin, Texas

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Today

Description: Experience in PCB ECAD design using Cadence Allegro V17.2 / 17.4 (Mandatory) Knowledge in PCB eCAD & Library using Cadence allegro eCAD tool. Experience in Constraints editor System, Strong Design knowledge from schematics to Gerber. Experience in Digital, Analog & Mixed signal designs. Knowledge on Routing High speed PCB, Power plane, Creepages and clearance, length matching Knowledge on High speed interfaces such (SATA, DDR4, DDR5, USB, Ethernet, PCIe, PMIC etc) Knowledge on RF bo

Full-time

USD120000.0/ANNUAL - USD130000.0/ANNUAL

Senior DFT Engineer

Santa Clara, California

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Today

Come be a part of new process technology adoption by joining NVIDIA's Advanced Technology Group! Work as part of the advanced technology team to optimize design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior DFT Engineer to join our dynamic and growing team! If you are problem solver and highly motivated individual searching for a collaborative and exciting role, join us today. We encourage applicants with a history of proven success working in a multic

Full-time

USD 196,000.00 - 310,500.00 per year

ASIC Design Engineer

No location provided

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Today

JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and internal IP's. Successful candidates will be responsible for leading, and participating in, the design of leading edge SoC's in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-a

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Full-time, Contract, Third Party

Principal / Lead Design Engineer – Memory Controller (CHI-G / DFI)

San Jose, California

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2d ago

Principal / Lead Design Engineer Memory Controller (CHI-G / DFI) Were looking for an experienced Principal / Lead Design Engineer to lead RTL development and architecture updates for our Memory Controller subsystem, with strong expertise in ARM CHI-G (Coherent Hub Interface Gateway) and DDR/LPDDR/HBM PHY-facing DFI. Key Responsibilities: Modify and extend existing Memory Controller RTL for new CHI-G and DFI requirements Drive microarchitecture updates for command scheduling, arbitration, Qo

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Contract

Depends on Experience

PCB Layout Engineer

San Francisco, California

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10d ago

PCB Layout Engineer (High-Speed Server Board Design)Location: Bay Area, CA (Onsite) Duration: 6+ Months (Contract) Job SummaryWe are seeking an experienced PCB Layout Engineer with strong expertise in high-speed PCB layout and server board design. The ideal candidate will have hands-on experience designing complex multilayer server boards and be highly proficient in Cadence Allegro PCB Designer version 22.1 or higher. This role requires close collaboration with hardware, signal integrity, power

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Contract

55 - 58

DRAM Architect - Sr Engineer

Boise, Idaho

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary As a DRAM Architect, you will optimize DRAM solutions for power, performance, and cost while pioneering new memory features and system-level innovations. You will collaborate with glob

Full-time

Design Verification Engineer

San Diego, California

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19d ago

Design Verification EngineerLocation: Bay Area, CA (Onsite/Hybrid) Experience: 8+ Years Job SummaryWe are seeking an experienced Design Verification Engineer with strong expertise in ASIC/SoC verification to join our semiconductor team. The ideal candidate will have extensive experience in SystemVerilog, UVM, and protocol verification, with a proven track record of developing robust verification environments and achieving coverage closure. Key ResponsibilitiesDevelop and execute comprehensive ve

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Full-time, Third Party

180,000 - 200,000

Sr Design Engineer, HBM

Richardson, Texas

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron?s Heterogeneous Integration Group (HIG) is shaping the future of AI and accelerated computing by developing advanced memory solutions! The team focuses on designing and optimizing High Band

Full-time

DRAM Memory Design Engineer - Principal | MTS | SMTS

Boise, Idaho

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are shaping the memory technologies that power today\'s most advanced computing platforms, from AI accelerators to mobile and client devices. Our DRAM Engineering team brings together skilled e

Full-time

Lead MTS Applications Engineering

San Jose, California

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Today

Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead MTS Application Engineer to join our Memory Interface team in San Jose California. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As a Lead MTS Application engineer, the candidate will be reporting to Director of Application and Validation and is a Full-Time position. The engineer will work on developing the v

Full-time

USD 117,300.00 - 167,500.00 per year

Test Engineer-Various Levels

San Jose, California

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Today

Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire exceptional Test Engineers to join our Operations team in San Jose. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per wee

Full-time

USD 126,000.00 - 234,000.00 per year

SPE Analog Engineering

Johns Creek, Georgia

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Today

Overview The candidate will be part of Rambus Memory Interface Chips BU's design group responsible for specifying, architecting, executing, and productizing leading edge memory interface buffer chips for DDR5, DDR6 and beyond. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Owner and domain expert of anal

Full-time

USD 169,400.00 - 254,000.00 per year

Staff DDR Analog Characterization Engineer

Chandler, Arizona

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Today

Come break new ground in Post-Silicon Characterization with our diverse, engineering-centric team! This is a rare opportunity to join the Chandler Post-Silicon Characterization team. Our team validates and characterizes industry-leading Arm SoCs and enables our customers to bring world-changing products to market. As a Staff DDR Analog Characterization Engineer, you will join a cooperative group of engineers tasked with validating and characterizing next-generation DDR memory interfaces. You w

Full-time

USD 198,100.00 - 268,000.00 per year

Senior / Principal Layout Engineer - Module Architecture (Pathfinding)

San Jose, California

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking a Senior / Principal Layout Engineer to drive pathfinding and architecture exploration for next-generation memory modules and form factors (DDR6, LPDDR6/LPDDR7, MRDIMM Gen3/Gen4, SOC

Full-time

USD 202,000.00 - 344,000.00 per year

PE Product Engineering

San Jose, California

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Today

Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Product Engineering to join our Operations Engineering team in San Jose. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. As a Product Engineer, you will play a key role in new product introduction. In this full-time position, you will report directly to the Senior Manager of

Full-time

USD 124,000.00 - 230,400.00 per year

Electrical Senior Engineer

Round Rock, Texas

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Today

Job Description Infrastructure Solutions Group (ISG) builds the products that power infrastructure, solutions, and data management our customers need most. Our teams design and develop the hardware and software that connect infrastructure, accelerate computational workloads, integrate across the stack, protect data continuity, and deliver the platforms, applications, and diagnostics our customers rely on every day at enterprise scale. Some product builders follow the rules. Ours rewrite them.

Full-time

USD 131,000.00 - 170,000.00 per year