DDR SDRAM jobs in Palo Alto, CA

Signal Integrity Engineer ? DRAM Product Architecture for AI Systems

San Jose, California

•

Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are the Compute and Memory Business Unit (CMBU), driving the innovation behind Micron\'s next generation DRAM solutions for AI, data center, and client computing platforms. Our team collaborate

Full-time

Compensation information provided in the description

Hardware Engineer

Cupertino, California

•

Today

Location: Cupertino, CA Salary: $120,000.00 USD Annually - $130,000.00 USD Annually Description: Hardware Engineer San Jose, CA Fulltime Hardware Engineer - High Speed Complex Hardware Design and Failure Analysis High Speed Complex Hardware Design and Failure Analysis experience Must have 8+ yrs experience in the hardware design, specific networking or equally complex products Hands on with Hardware design with interfaces - High Speed SERDES (>25G), PCIe Gen 5 and above and experience wit

Full-time

USD 120,000.00 - 130,000.00 per year

Hardware Design Engineer

San Jose, California

•

Today

The following requirement is open with our client. Job Title : Hardware Design Engineer Location : San Jose CA (Onsite) Rate : $75/c2c or $70/w2 (All Inclusive) Relevant Experience (in Yrs.): 10+ Job Description: Seeking an experienced Hardware Design and Failure Analysis Engineer with 10 years of experience in hardware engineering, board design, and system-level failure analysis. Must have expertise in high-speed interfaces, power and signal integrity, and component-level failure analysis. Resp

Easy Apply

Full-time

Depends on Experience

PCB Layout Engineer

Menlo Park, California

•

10d ago

Job Description: Must have : Allegro PCB and CAD Software Key Responsibilities Own end-to-end PCB layout for complex, high-density designs used in data center server boardsPerform high-speed digital layout for interfaces like HBM,DDR4/5, PCIe Gen 5/6, USB 3.2 or higher, with attention to controlled impedance, length matching, and crosstalk mitigationDevelop and enforce layout design rules for High-speed digital, analog, mixed-signal, and power domains within tightly constrained wearable form fac

Easy Apply

Full-time, Third Party

Depends on Experience

Memory PHY Firmware Architect

Santa Clara, California

•

Today

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you're designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Joi

Full-time

USD 179,900.00 per year

Signal Integrity Engineer

Santa Clara, California

•

Today

Description Invent the future with us. Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AI compute . As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications. Join us at Ampere and work alongside a passionate and growing team - we'd

Full-time

USD 159,000.00 - 239,000.00 per year

Test Engineer-Various Levels

San Jose, California

•

Today

Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire exceptional Test Engineers to join our Operations team in San Jose. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per wee

Full-time

USD 126,000.00 - 234,000.00 per year

PE Validation Engineering

San Jose, California

•

Today

Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Validation Engineer to join our Memory Interface Chip business unit. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. The PE Validation Engineer is a Full-Time position, and the candidate will work in the lab to automate data collection and provide framework to develop validation environment to check system

Full-time

USD 140,800.00 - 261,600.00 per year

CPU Post-Silicon Performance Engineer

Santa Clara, California

•

Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: As a "CPU Silicon Bring up and Validation Engineer" you would be part of the CPU Silicon Bringup Team, within the CPU team. The charter for CPU Silicon Bringup team would be to prepare for and support bring up of every SoC using the Custom CPUs - from first Silicon through to productization. Roles and Responsibilities: Work with CPU design and verification teams to develop CP

Full-time

USD 147,900.00 - 221,900.00 per year

Tech Dir Validation Engineering

San Jose, California

•

Today

Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Technical Director Validation Engineer to join our Memory Interface Chip business unit. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. The Technical Director Validation Engineer is a Full-Time position and the candidate will work in the lab to automate data collection and provide framework to develop validation env

Full-time

USD 189,000.00 - 351,000.00 per year

MTS Validation Engineering

San Jose, California

•

Today

Overview Rambus, a premier chip and silicon IP provider, is seeking to hire a System Validation Engineer to join our Memory Interface Chip business unit. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. The System Validation Engineer is a Full-Time position, and the candidate will work in the lab to execute server system validation, automate data collection, develop validation environment, and check system

Full-time

USD 84,800.00 - 157,600.00 per year

Prinicipal Signal Integrity Engineer

San Jose, California

•

Today

Full-time

USD 203,000.00 per year

Hardware Design Integrity Engineer

Santa Clara, California

•

Today

Company Description Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. What sets us apart is our relentless pursuit of innovation. We leverage the latest advancements in cloud computing, artificial intelligence, and software-defined networking to provide our clients with a competitive edge in an increasingly interconnected world. Our solutions are designed to not only meet the current demands of the digital la

Full-time

USD 130,000.00 - 225,000.00 per year

Senior ATE Test Engineer

San Jose, California

•

Today

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-t

Full-time

USD 135,500.00 - 170,000.00 per year

Principal Hardware Validation Engineer

San Jose, California

•

Today

Full-time

USD 185,000.00 per year

Lead MTS Applications Engineering (EE, CE, CS New Grads Welcome)

San Jose, California

•

Today

Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead MTS Application Engineer to join our Memory Interface team in San Jose California. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As a Lead MTS Application engineer, the candidate will be reporting to Director of Application and Validation and is a Full-Time position. The engineer will work on developing the v

Full-time

USD 117,300.00 - 167,500.00 per year

Hardware Design Engineer 4

Santa Clara, California

•

Today

Job Description THE ROLE: As a member of the CT Server DDR team, we are looking for an experienced signal integrity and power integrity engineer who can be responsible for DDR PHY channel and power delivery network (PDN) architecture, system-level SI/PI, and post-silicon validation. THE PERSON: The engineer needs to be hands-on in defining channel and PDN architectures, modeling signal and power delivery at the system level, and validating SI/PI on silicon. The engineer needs to work with desi

Full-time

Full Chip Timing Modeling and Integration Engineer

San Jose, California

•

Today

Job Details: Job Description: About the Role Altera is seeking highly qualified candidates to join our Full Chip Timing team. Altera continues to deliver industry-leading Field-Programmable Gate Array (FPGA) solutions to customers. As a Full Chip Timing Modeling and Integration Engineer, you will develop timing methodologies and execute full-chip timing for Altera's next-generation product lines using the world's most advanced process technologies. This is a fast-paced, dynamic environment

Full-time

USD 133,200.00 - 192,825.00 per year

Principal Hardware Engineer

San Jose, California

•

Today

Company Description Axiado is an AI-enhanced security processor company redefining the control and management of every digital system. The company was founded in 2017, and currently has 100+ employees. At Axiado, developing great technology takes more than talent: it takes amazing people who understand collaboration, respect each other, and go the extra mile to achieve exceptional results. It takes people who have the passion and desire to disrupt the status quo, deliver innovation, and change

Full-time

SoC DRAM Memory Subsystem Validation Engineering Program Manager

Cupertino, California

•

Today

Come and join the team that crafts Apple's groundbreaking silicon. Apple makes the greatest SoCs in the world; to do that takes thousands of employees, multiple years and very significant R&D spending. To make the best use of those employees, time, and money requires excellent methodologies and structures. As we continue to expand and mature, the processes used to develop these SOCs must be improved. Join us to do your life's best work in this rare opportunity to help define the next big thing t

Full-time

DDR SDRAM jobs in Palo Alto, CA, USA