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Role: Staff Machine Learning Engineer Location: San Jose, CA (Onsite) Locals Duration: Long-term Why this role exists We're building privacy preserving LLM capabilities that help hardware design teams reason over Verilog/SystemVerilog and RTL artifacts-code generation, refactoring, lint explanation, constraint translation, and spec to RTL assistance. We're looking for a Staff level engineer to technically lead a small, high leverage team that fine tunes and productizes LLMs for these workflows
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