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Responsibilities: Strong understanding in the RTL2GDSII flow and design tapeouts in 16nm/14nm or below process technologiesExperience with low power implementation, power gating, multiple voltage rails, strong UPF/CPF knowledge.Experience working with most EDA tools like DC/Genus, ICC2/Innovus, Primetime, PTPX, PrimepowerDuties: Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place an
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$95 - $115