Entry Level Physical Design Engineer jobs

Physical Design Engineer/Static Timing Analysis Engineer

San Diego, California

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Today

Urgent position of Physical Design Engineer/Static Timing Analysis Engineer Location San Diego,CA(Onsite) Duration- Long Term We are hiring Static Timing Analysis engineers to strengthen the timing signoff team supporting a leading SoC manufacturer on advanced-node designs. In this role you will own timing constraints, drive block- and full-chip timing closure across all modes and corners, and collaborate closely with the physical design, synthesis, and DFT teams to deliver clean, silicon

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Contract, Third Party

$60 - $65

Physical Design Engineer

San Jose, California

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Today

Title :: Physical Design Engineer Location :: San Jose, CA Job Type:- Full Time We are seeking a Physical Design Engineer with extensive industry experience to join our world-class silicon engineering team in Sunnyvale, California. This role is designed for highly accomplished engineers who have successfully delivered multiple complex SoCs from architecture through tapeout in advanced technology nodes (7nm, 5nm, 3nm, and below). You will work closely with Architecture, RTL, DFT, Logic Design,

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Full-time

$market rate

ASIC Physical Design Engineer

San Jose, California

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Today

Hiring: ASIC Physical Design Engineer Location: San Jose, CA(onsite) Experience: 7 to 12 years This requirement is similar to Physical Design Requirement (PD Engineer).Job Responsibilities: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.Help close EM/IR, drive LEC and physical verification signoff for y

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Contract, Third Party

$60 - $65

ASIC Physical Design Engineer

San Jose, California

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4d ago

Hiring:ASIC Physical Design EngineerLocation: San Jose, CA(onsite)Experience: 7 to 12 yearsThis requirement is similar to Physical Design Requirement (PD Engineer).Job Responsibilities: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.Help close EM/IR, drive LEC and physical verification signoff for your

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Third Party, Contract

$60 - $70

Physical Design Engineer

Mountain View, California

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3d ago

Hi, Job Title: Physical Design Engineer (PnR / PPA / Timing Closure) Location : Mountain View, CA Responsibilities: We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Preferred Qualifications: Bachelor's or Master's degree in Electrical/Electronics Engineering.Experience in advanced nodes (7nm/5nm/3nm preferred).Strong debugging and problem-solving skills.Exp

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Full-time, Third Party

Depends on Experience

Senior ASIC Physical Design Engineer - W2 Role - 100% Remote (US)

Remote or Arkansas

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Today

Role: Senior ASIC Physical Design Engineer 100% Remote (US) Job Type: W2 Contract Must Have: Experience taking a design through the full lifecycle on real hardware (FPGA, SoC, or ASIC) About the Role: You will join a digital hardware team and contribute across the full silicon development lifecycle - from preliminary analysis and micro-architecture definition through RTL development, functional verification, ASIC/FPGA/SoC implementation, on-hardware bring-up, and design documentation. Engineers

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Contract

Physical Design Engineer & DV Engineers

Sunnyvale, California

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Today

Job Title:PhysicalDesignEngineer(PD/PnR) Location Bay Area CA / Austin TX (Hybrid) Job Summary Seeking aPhysicalDesignEngineerwith strong hands-on experience in block-level and top-level Place & Route using Synopsys Fusion Compiler. The candidate will be responsible for implementation, timing closure, low-power integration, and signoff activities for complex SoCdesigns. Key Responsibilities Perform block-level and top-levelPhysicalDesignimplementation using Fusion Compiler. Drive floorplannin

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Full-time

160,000 - 170,000

Physical Design Engineer

Sunnyvale, California

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Today

Title :: Physical Design Engineer Location :: Sunnyvale, CA(Onsite) We are seeking a Physical Design Engineer with extensive industry experience to join our world-class silicon engineering team in Sunnyvale, California. This role is designed for highly accomplished engineers who have successfully delivered multiple complex SoCs from architecture through tapeout in advanced technology nodes (7nm, 5nm, 3nm, and below). You will work closely with Architecture, RTL, DFT, Logic Design, Packaging,

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Full-time

$130000 - $150000

Physical Design Engineer

Mountain View, California

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26d ago

Physical Design Engineer (PD / PnR / PPA / Timing Closure) Location: Mountain View CA (Onsite) Job Description We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floor planning, power planning, placement, clock tree synthesis (CTS), routing, and physical veri

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Contract

Depends on Experience

Physical Design Engineer

Austin, Texas

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Today

About US Visara Partners is built on the belief that human potential and organizational intelligence can be architected, scaled, and sustained with intention. We harmonize human intelligence with artificial intelligence to design organizations that think, adapt, and grow with purpose. Job DescriptionSeeking an experienced Physical Design Engineer with expertise in advanced-node implementation and physical design closure. ResponsibilitiesFloorplanningPlacementCTSRoutingTiming ClosurePhysical Ver

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Full-time

130,000 - 140,000

Physical Design Engineer (PnR / PPA / Timing Closure) (Only W2))

Mountain View, California

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7d ago

Job Description We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification. Optimize designs for Power, Performance, and Area (PPA) targets. Achieve timing closure

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Full-time

140,000 - 150,000

Front End Physical Design Engineer at Sunnyvale, CA

Sunnyvale, California

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7d ago

Front End Physical Design Engineer at Sunnyvale, CAIntroductionThis position is for a Front End Physical Design Engineer based in Sunnyvale, CA. The successful candidate will be responsible for driving RTL synthesis and optimization to achieve performance, power, and area goals for complex ASIC/SoC designs. They will work closely with various teams to ensure optimal timing, congestion, and power distribution in the design. ResponsibilitiesDrive RTL synthesis and optimization to achieve performan

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Full-time, Third Party

150,000 - 160,000

Physical Design Engineer II (eInfochips Inc)

San Jose, California

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Today

Position:Physical Design Engineer II (eInfochips Inc) Job Description:WhatYou\'llBeDoing: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.Partner with the design team to proactively id

Full-time

ASIC Physical Design Engineer

New York, New York

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18d ago

About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test, and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to collaborate with people in areas across the firm, including trading, networking, and research infrastructure. This isn't a traditional PD role. We're a small team where everyone works across the chip design process, and we expect our PD engineers to lead with physical design expertise but think like

Full-time

Junior Engineer (Design)

New York, New York

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Today

Company Description Job Description Hours: Full-Time - 35 Hours Work Location: 30-30 Thomson Avenue, LIC, NY 11101 All interested candidates are welcome to apply and will be considered for an interview based on the Minimum Qualification. Please indicate on your Cover Letter if you are permanent in the civil service title of Civil Engineer Intern or if you are on the open-competitive list for exam #5047. The Department of Design & Construction, Division of Infrastructure, is currently seeking

Full-time

USD 60,000.00 - 70,000.00 per year

SoC Physical Design Engineer, Electrical Analysis

Austin, Texas

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Today

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our pr

Full-time

Senior Staff GPU Physical Design Engineer

Remote

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Today

Job Description Title: Senior Staff GPU Physical Design Engineer Location: Austin, TX or San Jose, CA. onsite strongly preferred Need: GPU or high-performance SoC experience. Advanced node (?5nm). Full block ownership Position Summary We are seeking a Senior Staff GPU Physical Design Engineer for our client to work on the physical implementation of high-performance GPU and system-level IP, driving execution across synthesis, place-and-route, timing closure, and signoff for their advanced tech

Contract

Entry Level Engineer # 26-17533

Hybrid in Birmingham, Alabama

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Today

Duration: 5 Months Job Description: The Engineer 1 position requires 0-5 years of related experience and an accredited bachelors degree. Responsible for applying engineering processes, design criteria, and software applications to design and construct power related systems. Supports estimate preparation, develops design options, and prepares construction specifications. Provide guidance, oversight, and quality assurance reviews for approved contractors as they develop design solutions, cost

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Contract

$35 - $40

Entry Level Structures Design Engineer

North Charleston, South Carolina

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Today

Job Description At Boeing, we innovate and collaborate to make the world a better place. We?re committed to fostering an environment for every teammate that?s welcoming, respectful and inclusive, with great opportunity for professional growth. Find your future with us. Boeing Commercial Airplanes is looking for Entry Level Structures Design Engineers to work at our Ladson, SC location. At Boeing, our engineers share a passion to redefine what?s possible. To turn dreams into reality. To bring cu

Full-time

Compensation information provided in the description

Entry-Level Mechanical Product Design and Analysis Engineer

El Segundo, California

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Today

Entry-Level Mechanical Product Design and Analysis Engineer Company: The Boeing Company Boeing Space, Intelligence & Weapons Systems is currently hiring an Entry-Level Space Electronics Packaging and Mechanical Product Design and Analysis Engineer to join us as part of our Electronics Packaging and Product Design Team located in El Segundo, CA. We are seeking exceptional Mechanical Engineers with a passion for innovation to join our team and become part of something truly remarkable. As a Spa

Full-time

USD 79,050.00 - 106,950.00 per year

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Entry Level Physical Design Engineer jobs