Entry Level Physical Design Engineer jobs

Sr. Physical Design Engineer, Amazon Leo

Austin, Texas

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Today

Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.Be part of Amazon Leo?s sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with cus

Full-time

Sr. Physical Design Engineer, Amazon Leo

Austin, Texas

•

Today

Full-time

Physical Design Engineer

Sunnyvale, California

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11d ago

Hi Good Morning, Job Title: Physical Design Engineer Location- Sunnyvale, CA- Onsite Need a PDE with front end experience who is good with Synthesis, PDE flow and placement optimization. We are hiring an experienced Physical Design Engineer to join a high-performing silicon engineering team supporting one of the world's leading technology organizations in Sunnyvale, CA. This is an exciting opportunity to work on cutting-edge ASIC/SoC designs and collaborate with talented engineers throughout the

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Contract, Third Party

Physical Design Engineer

Remote

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Yesterday

Role: Physical Design Engineer Client: Broadcom Employment Type: Full-Time Locations: San Jose, CA / San Diego, CA / Irvine, CA Experience: 12+ Years Salary Range: $130,000 - $190,000 per annum Key Responsibilities Execute end-to-end Physical Design, Synthesis, Physical Verification, and Timing Closure activities. Setup and synthesize RTL designs. Perform timing closure using various methodologies and strategies, including top-level STA. Conduct EM/IR analysis. Execute Place & Route (P&R). Deve

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Contract

18 - 135

SR PHYSICAL DESIGN ENGINEER _ FULL TIME

Sunnyvale, California

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3d ago

TITLE: SR PHYSICAL DESIGN ENIGNEER LOCATION: SUNNYVALE, CA (ONSITE) FULL TIME ROLE Senior ASIC/SoC Physical Design Engineer with 10+ years of experience who has strong hands-on expertise in RTL synthesis, optimization, and floor planning. The candidate should be capable of optimizing chip designs for Power, Performance, and Area (PPA), improving timing and congestion, analyzing netlists, and supporting timing closure. Must have experience working closely with RTL design, verification, and physic

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Full-time

Depends on Experience

Physical Design Engineer

Austin, Texas

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4d ago

Hi, Job Title: Physical Design Engineer Location : Austin ,TX / San Diego and Santa Clara , CA Responsibilities: We are seeking an experienced Physical Design Engineer to work on advanced semiconductor designs, including ASIC/SoC implementation, timing optimization, and physical design signoff. Thanks & Regards, Preethi S Reveille Technologies Inc.,

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Contract

Depends on Experience

Physical Design Engineer

Hybrid in San Jose, California

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Today

Title: Physical Design Engineer Location: San Jose, CA and Austin, TX (Hybrid 3 days Onsite) Duration: 12 months Interview: MS Teams Job Summary: Responsibilities We are seeking a Physical Design contractor with strong synthesis and implementation expertise to support large, timing-critical designs at advanced technology nodes. Key Responsibilities: Perform synthesis using Cadence Genus for large, timing-challenged designsDrive PPA (power, performance, area) optimization through synthesis an

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Contract, Third Party

Depends on Experience

Physical Design Engineer

Palo Alto, California

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4d ago

JD for PD: Exposure to TSMC 2NP/3NP is mustPerform endtoend physical design flow:FloorplanningPower planning (PG grid, IR)Placement & optimizationCTS (Clock Tree Synthesis)RoutingPostroute optimizationAchieve timing closure across all modes and cornersResolve DRC, LVS, ERC and signoff violationsHandle lowpower design techniques:MultiVt, Multivoltage (UPF)Power gating, clock gatingPerform physical verification and signoff:STA (Primetime)SI / CrosstalkIR drop & EM analysisWork on advanced nodes (7

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Contract

Depends on Experience

Physical Design Engineer

Austin, Texas

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4d ago

What You'll Be Doing: RTL to Physical Design (RTL2PD) stage experienceRTL2PD Design Engineer(ASIC)MUST HAVE : RTL Synthesis, Constraint writing, validation, Static timing AnalysisRTL Synthesis, Constraint writing, validation, Static timing AnalysisWriting Scripts/Modiying scripts for RTL synthesis, SDC creation, STADebug synthesis issues and STAGenerate clean netlist. What we are looking for: Experience: 5+ years of hands-on RTL SynthesisEDA exposure: Design compiler, PrimeTime, Tempus, Genus,Mu

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Contract, Third Party

$50 - $60

Physical Design Engineer Semiconductor / ASIC

Hybrid in Palo Alto, California

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18d ago

Physical Design Engineer Semiconductor / ASIC Location: Palo Alto, CA (100% Onsite) Openings: 5 Job Overview We are looking for an experienced Physical Design Engineer with strong hands-on expertise in end-to-end ASIC physical design and advanced semiconductor process nodes. The ideal candidate must have exposure to TSMC 2NP/3NP technology and proven experience in physical implementation, timing closure, power optimization, and physical verification. Key Responsibilities Execute the complete phy

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Contract

$70 - $90

Physical Design Engineer

Sunnyvale, California

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11d ago

Job Title: Physical Design Engineer Location- Sunnyvale, CA- Onsite Need a PDE with front end experience who is good with Synthesis, PDE flow and placement optimization. Key Responsibilities Drive RTL synthesis and optimization to achieve performance, power, and area (PPA) goals Perform floor planning for complex ASIC/SoC designs while ensuring optimal timing, congestion, and power distribution Collaborate closely with RTL design engineers to provide actionable feedback that improves RTL qualit

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Contract, Third Party

Physical Design Engineer

Remote

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6d ago

Job Title: Physical Design Engineer Location: Remote We are looking for a Physical Design Engineer with hands-on experience in TSMC 3nm/2nm at SOC for cutting-edge GPU / High-Performance designs. Key Responsibilities: 1. Own Netlist-to-GDSII for high-speed, low-power SOC 2. Floorplanning, Placement, CTS, Routing, Timing closure 3. Drive PPA optimization - Power, Performance, Area for 2nm/3nm 4. Handle advanced nodes issues: IR Drop, EM, Crosstalk etc 5. Hands on experience on tools - Synopsys F

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Contract, Third Party

$60+

Physical Design Engineer GPU / High-Performance SoC

Remote

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18d ago

Job Title: Physical Design Engineer GPU / High-Performance SoC Location: Mountain View, CA (Full Onsite) Openings: 2 Job Description We are looking for an experienced Physical Design Engineer with hands-on experience in advanced semiconductor process nodes, particularly TSMC 3nm and/or 2nm, for high-performance SoC, GPU, or similar complex chip designs. The ideal candidate will have strong end-to-end physical design experience, from netlist to GDSII, along with expertise in PPA optimization, tim

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Contract

$60 - $80

Physical Design Engineer

Austin, Texas

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30+d ago

Job Description We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification. Optimize designs for Power, Performance, and Area (PPA) targets. Achieve timing clo

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Full-time

Depends on Experience

Physical Design Engineer

Remote

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4d ago

Physical Design (Place & Route) Engineer Fully remoteDuration: Long term contractAbout the RoleOur ASIC team is hiring a seasoned Place and Route (P&R) Engineer to own the physical implementation of complex, high-performance chips. You will take designs from a synthesized netlist all the way to final GDSII, pushing hard on power, performance and area (PPA) while protecting design integrity, manufacturability and the schedule.What Youll DoRun full-chip physical implementation from netlist to GDSI

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Contract

100 - 110

Physical Design Engineer

Hybrid in Sunnyvale, California

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4d ago

We are hiring an experienced Physical Design Engineer to join a high-performing silicon engineering team supporting one of the world's leading technology organizations in Sunnyvale, CA. This is an exciting opportunity to work on cutting-edge ASIC/SoC designs and collaborate with talented engineers throughout the chip development lifecycle. Key Responsibilities Drive RTL synthesis and optimization to achieve performance, power, and area (PPA) goals Perform floorplanning for complex ASIC/SoC de

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Third Party, Contract

Depends on Experience

Senior Physical Design Engineer

Sunnyvale, California

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Today

I hope this message finds you well and thriving. We are currently seeking a highly skilled and experienced Physical Design Engineer to join a high-performing silicon engineering team supporting one of the world's leading technology organizations in Sunnyvale, CA. This is an exciting opportunity to work on cutting-edge ASIC/SoC designs and collaborate with talented engineers throughout the chip development lifecycle. Job Title: Senior Physical Design Engineer Location: Sunnyvale, CA Job Type: Fu

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Full-time

180,000 - 200000

Physical Design Engineer

Remote

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4d ago

WE'RE HIRING | PHYSICAL DESIGN ENGINEERS Locations: San Jose, CA / San Diego, CA / Irvine, CA Experience: 12+ Years Employment Type: Full-Time We are looking for experienced Physical Design Engineers with strong expertise in ASIC/SoC Physical Design and end-to-end RTL-to-Tape-out implementation. Key Responsibilities: Execute end-to-end Physical Design, Synthesis, Physical Verification, and Timing Closure. Perform RTL synthesis and Static Timing Analysis (STA). Execute Place & Route (P&R) and Clo

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Full-time

150,000 - 170,000

Physical design engineer - Boston, MA

Boston, Massachusetts

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4d ago

Design Verification Engineer|| Location Boston, MA || Employment type contract Job Description: Senior DV engineers that have substantial experience with C++. C++ will be used verification (via teal/truss) and not SV/UVM Ideally, the candidates would have experience with either DSP and/or Ethernet protocols. Experience: 8+ yrs (mandatory)

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Third Party, Contract

$55 - $65

Physical Design Engineer

Sunnyvale, California

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17d ago

Role : Physical Design EngineerLocation- Sunnyvale, CA- OnsiteNeed a PDE with front end experience who is good with Synthesis, PDE flow and placement optimization.We are hiring an experienced Physical Design Engineer to join a high-performing silicon engineering team supporting one of the world's leading technology organizations in Sunnyvale, CA. This is an exciting opportunity to work on cutting-edge ASIC/SoC designs and collaborate with talented engineers throughout the chip development lifecy

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Third Party, Contract

Depends on Experience