Entry Level Physical Design Engineer jobs

Sr. Physical Design Engineer, Amazon Leo

Austin, Texas

•

Today

Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.Be part of Amazon Leo?s sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with cus

Full-time

Sr. Physical Design Engineer, Amazon Leo

Austin, Texas

•

Today

Full-time

Physical Design Engineer

Austin, Texas

•

Yesterday

Hi, Job Title: Physical Design Engineer Location : Austin ,TX / San Diego and Santa Clara , CA Responsibilities: We are seeking an experienced Physical Design Engineer to work on advanced semiconductor designs, including ASIC/SoC implementation, timing optimization, and physical design signoff. Thanks & Regards, Preethi S Reveille Technologies Inc.,

Easy Apply

Contract

Depends on Experience

Physical design Engineer

Mountain View, California

•

18d ago

Position 1 Physical Design Engineer Mountain View CA (onsite - Hybrid) Mode of hiring: Fulltime permanent Customer wants someone who is having some logical design experience along with PD experience. Having some RTL2PD flow skills such as CDC/RDC/VCLP is preferred. Having some exposure of logic design is also preferred. Canddiate doesn't have to do the logic design, but needs to review the synthesis/PNR report to analyze for the timing/LoL optimization Provides services in transforming the RTL d

Easy Apply

Full-time

$120,000 - $140,000

Physical Design Engineer Semiconductor / ASIC

Hybrid in Palo Alto, California

•

4d ago

Physical Design Engineer Semiconductor / ASIC Location: Palo Alto, CA (100% Onsite) Openings: 5 Job Overview We are looking for an experienced Physical Design Engineer with strong hands-on expertise in end-to-end ASIC physical design and advanced semiconductor process nodes. The ideal candidate must have exposure to TSMC 2NP/3NP technology and proven experience in physical implementation, timing closure, power optimization, and physical verification. Key Responsibilities Execute the complete phy

Easy Apply

Contract

$70 - $90

Physical Design Engineer

Palo Alto, California

•

Yesterday

JD for PD: Exposure to TSMC 2NP/3NP is mustPerform endtoend physical design flow:FloorplanningPower planning (PG grid, IR)Placement & optimizationCTS (Clock Tree Synthesis)RoutingPostroute optimizationAchieve timing closure across all modes and cornersResolve DRC, LVS, ERC and signoff violationsHandle lowpower design techniques:MultiVt, Multivoltage (UPF)Power gating, clock gatingPerform physical verification and signoff:STA (Primetime)SI / CrosstalkIR drop & EM analysisWork on advanced nodes (7

Easy Apply

Contract

Depends on Experience

Physical Design Engineer

Sunnyvale, California

•

Today

Job Title: Physical Design Engineer Location: San Jose, CA Job Description: Need a PDE with front end experience who is good with Synthesis, PDE flow and placement optimization. We are hiring an experienced Physical Design Engineer to join a high-performing silicon engineering team supporting one of the world's leading technology organizations in Sunnyvale, CA. This is an exciting opportunity to work on cutting-edge ASIC/SoC designs and collaborate with talented engineers throughout the chip de

Easy Apply

Full-time, Part-time, Third Party, Contract

Physical Design Engineer GPU / High-Performance SoC

Remote

•

4d ago

Job Title: Physical Design Engineer GPU / High-Performance SoC Location: Mountain View, CA (Full Onsite) Openings: 2 Job Description We are looking for an experienced Physical Design Engineer with hands-on experience in advanced semiconductor process nodes, particularly TSMC 3nm and/or 2nm, for high-performance SoC, GPU, or similar complex chip designs. The ideal candidate will have strong end-to-end physical design experience, from netlist to GDSII, along with expertise in PPA optimization, tim

Easy Apply

Contract

$60 - $80

VLSI Physical Design Engineer (California, Texas) - W2 Only

Austin, Texas

•

6d ago

Hello, Hope you are doing good ! Please find the JD below and share your updated resume POSITION: VLSI Physical Design Contractor Location: San Jose, CA and Austin, TX Responsibilities We are seeking a Physical Design contractor with strong synthesis and implementation expertise to support large, timing-critical designs at advanced technology nodes. Key Responsibilities: Perform synthesis using Cadence Genus for large, timing-challenged designs Drive PPA (power, performance, area) optimization

Easy Apply

Full-time

$60 - $70

Physical Design Engineer

Remote

•

Today

Job Title: Physical Design Engineer Location: Remote We are looking for a Physical Design Engineer with hands-on experience in TSMC 3nm/2nm at SOC for cutting-edge GPU / High-Performance designs. Key Responsibilities: 1. Own Netlist-to-GDSII for high-speed, low-power SOC 2. Floorplanning, Placement, CTS, Routing, Timing closure 3. Drive PPA optimization - Power, Performance, Area for 2nm/3nm 4. Handle advanced nodes issues: IR Drop, EM, Crosstalk etc 5. Hands on experience on tools - Synopsys F

Easy Apply

Contract, Third Party

$60+

Sr. Physical Design Engineer, Amazon Leo

Austin, Texas

•

Yesterday

Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. Be part of Amazon Leo's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with c

Full-time

USD 185,200.00 - 250,000.00 per year

Physical Design Engineer

Austin, Texas

•

30+d ago

Job Description We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification. Optimize designs for Power, Performance, and Area (PPA) targets. Achieve timing clo

Easy Apply

Full-time

Depends on Experience

Physical Design Engineer

Hybrid in Sunnyvale, California

•

5d ago

We are hiring an experienced Physical Design Engineer to join a high-performing silicon engineering team supporting one of the world's leading technology organizations in Sunnyvale, CA. This is an exciting opportunity to work on cutting-edge ASIC/SoC designs and collaborate with talented engineers throughout the chip development lifecycle. Key Responsibilities Drive RTL synthesis and optimization to achieve performance, power, and area (PPA) goals Perform floorplanning for complex ASIC/SoC de

Easy Apply

Contract, Third Party

Depends on Experience

Physical Design Engineer

Sunnyvale, California

•

3d ago

Role : Physical Design EngineerLocation- Sunnyvale, CA- OnsiteNeed a PDE with front end experience who is good with Synthesis, PDE flow and placement optimization.We are hiring an experienced Physical Design Engineer to join a high-performing silicon engineering team supporting one of the world's leading technology organizations in Sunnyvale, CA. This is an exciting opportunity to work on cutting-edge ASIC/SoC designs and collaborate with talented engineers throughout the chip development lifecy

Easy Apply

Contract, Third Party

Depends on Experience

Physical Design Engineer

Palo Alto, California

•

19d ago

Position: Physical Design Engineer Location : Palo Alto, CA (Full Onsite) Rate : 90-100/hr Client : HCL/Tesla Job ID : 166019 Number of Positions : 5 JD for PD: Exposure to TSMC 2NP/3NP is mustPerform endtoend physical design flow:FloorplanningPower planning (PG grid, IR)Placement & optimizationCTS (Clock Tree Synthesis)RoutingPostroute optimizationAchieve timing closure across all modes and cornersResolve DRC, LVS, ERC and signoff violationsHandle lowpower design techniques:MultiVt, Multivolta

Easy Apply

Contract

Depends on Experience

Physical Design Engineer – Lead

San Jose, California

•

18d ago

Position: Physical Design Engineer Lead Locations: San Jose, San Diego, Irvine, CA (Onsite) What You Will Do: Drive ASIC physical design implementation from floorplanning through signoff. Perform Place & Route (PnR), Clock Tree Synthesis (CTS), timing closure, and optimization. Achieve Power, Performance, and Area (PPA) targets. Develop and validate timing constraints and perform Static Timing Analysis (STA). Execute LEC, VCLP, and EMIR signoff activities. Collaborate with cross-functional

Easy Apply

Full-time

Depends on Experience

Physical Design Engineer with Cadence Innovus

San Jose, California

•

4d ago

Conduct EM/IR analysis.Strong experience with Cadence Innovus.Expertise in the complete Physical Design cycle from RTL to Tape-out.Strong TCL and/or PERL scripting skills.Develop and optimize Clock Tree Synthesis (CTS), including custom clock trees, insertion delay reduction, and skew balancing.Perform timing closure using various methodologies and strategies, including top-level STA.Collaborate closely with IC Design and RTL Engineering teams.

Easy Apply

Full-time

Depends on Experience

Physical Design Engineer (Top-Level / Full-Chip) - AS

San Jose, California

•

3d ago

Title: Physical Design Engineer/ ASIC Implementation Engineer (Strong Top-Level / Full-Chip Physical Design and Implementation experience) Location: San Jose, CA (Onsite role) Type: FTE Permanent role Note from Hiring manager: Candidate either should have good experience on Chip level/Top level design Or if they are extremely strong in one of the other aspects of design e.g. STA (Static Timing Analysis) or Floor Planning in chip design, they can still be considered. Only in those cases where y

Easy Apply

Full-time

Depends on Experience

Staff Physical Design Engineer, HBM

Richardson, Texas

•

Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron?s High?Bandwidth Memory (HBM) Digital Design organization is seeking a Digital Physical Design Engineer to drive backend implementation of high?performance, low?power digital logic used in

Full-time

Department Manager: Physical Design Engineer

Dallas, Texas

•

15d ago

Ready to make a difference? We are seeking a Department Manager, Substation Physical Engineering to lead and grow our substation engineering practice. In this leadership role, you will be responsible for the operational management, technical oversight, staff development, financial performance, and strategic growth of a department delivering substation physical engineering services to utility clients nationwide. You will provide leadership to a multidisciplinary team of substation physical engin

Full-time

USD 174,701.00 - 296,992.00 per year