Entry Level Physical Design Engineer jobs

Sr. Physical Design Engineer, Amazon Leo

Austin, Texas

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Today

Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.Be part of Amazon Leo?s sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with cus

Full-time

Sr. Physical Design Engineer, Amazon Leo

Austin, Texas

•

Today

Full-time

Physical Design Engineer

Austin, Texas

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2d ago

Hi, Job Title: Physical Design Engineer Location : Austin ,TX / San Diego and Santa Clara , CA Responsibilities: We are seeking an experienced Physical Design Engineer to work on advanced semiconductor designs, including ASIC/SoC implementation, timing optimization, and physical design signoff. Thanks & Regards, Preethi S Reveille Technologies Inc.,

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Contract

Depends on Experience

Physical design Engineer

Mountain View, California

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17d ago

Position 1 Physical Design Engineer Mountain View CA (onsite - Hybrid) Mode of hiring: Fulltime permanent Customer wants someone who is having some logical design experience along with PD experience. Having some RTL2PD flow skills such as CDC/RDC/VCLP is preferred. Having some exposure of logic design is also preferred. Canddiate doesn't have to do the logic design, but needs to review the synthesis/PNR report to analyze for the timing/LoL optimization Provides services in transforming the RTL d

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Full-time

$120,000 - $140,000

Physical Design Engineer Semiconductor / ASIC

Hybrid in Palo Alto, California

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3d ago

Physical Design Engineer Semiconductor / ASIC Location: Palo Alto, CA (100% Onsite) Openings: 5 Job Overview We are looking for an experienced Physical Design Engineer with strong hands-on expertise in end-to-end ASIC physical design and advanced semiconductor process nodes. The ideal candidate must have exposure to TSMC 2NP/3NP technology and proven experience in physical implementation, timing closure, power optimization, and physical verification. Key Responsibilities Execute the complete phy

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Contract

$70 - $90

Physical Design Engineer

Palo Alto, California

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2d ago

JD for PD: Exposure to TSMC 2NP/3NP is mustPerform endtoend physical design flow:FloorplanningPower planning (PG grid, IR)Placement & optimizationCTS (Clock Tree Synthesis)RoutingPostroute optimizationAchieve timing closure across all modes and cornersResolve DRC, LVS, ERC and signoff violationsHandle lowpower design techniques:MultiVt, Multivoltage (UPF)Power gating, clock gatingPerform physical verification and signoff:STA (Primetime)SI / CrosstalkIR drop & EM analysisWork on advanced nodes (7

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Contract

Depends on Experience

Physical Design Engineer

Sunnyvale, California

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2d ago

Job Title: Physical Design Engineer Location: San Jose, CA Job Description: Need a PDE with front end experience who is good with Synthesis, PDE flow and placement optimization. We are hiring an experienced Physical Design Engineer to join a high-performing silicon engineering team supporting one of the world's leading technology organizations in Sunnyvale, CA. This is an exciting opportunity to work on cutting-edge ASIC/SoC designs and collaborate with talented engineers throughout the chip de

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Full-time, Part-time, Third Party, Contract

VLSI Physical Design Engineer (California, Texas) - W2 Only

Austin, Texas

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4d ago

Hello, Hope you are doing good ! Please find the JD below and share your updated resume POSITION: VLSI Physical Design Contractor Location: San Jose, CA and Austin, TX Responsibilities We are seeking a Physical Design contractor with strong synthesis and implementation expertise to support large, timing-critical designs at advanced technology nodes. Key Responsibilities: Perform synthesis using Cadence Genus for large, timing-challenged designs Drive PPA (power, performance, area) optimization

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Full-time

$60 - $70

Physical Design Engineer

Remote

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2d ago

Job Title: Physical Design Engineer Location: Remote We are looking for a Physical Design Engineer with hands-on experience in TSMC 3nm/2nm at SOC for cutting-edge GPU / High-Performance designs. Key Responsibilities: 1. Own Netlist-to-GDSII for high-speed, low-power SOC 2. Floorplanning, Placement, CTS, Routing, Timing closure 3. Drive PPA optimization - Power, Performance, Area for 2nm/3nm 4. Handle advanced nodes issues: IR Drop, EM, Crosstalk etc 5. Hands on experience on tools - Synopsys F

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Contract, Third Party

$60+

Physical Design Engineer GPU / High-Performance SoC

Remote

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3d ago

Job Title: Physical Design Engineer GPU / High-Performance SoC Location: Mountain View, CA (Full Onsite) Openings: 2 Job Description We are looking for an experienced Physical Design Engineer with hands-on experience in advanced semiconductor process nodes, particularly TSMC 3nm and/or 2nm, for high-performance SoC, GPU, or similar complex chip designs. The ideal candidate will have strong end-to-end physical design experience, from netlist to GDSII, along with expertise in PPA optimization, tim

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Contract

$60 - $80

Physical design engineer

San Jose, California

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2d ago

Position - Physical design engineer - semiconductor Location - San Jose, CA (Onsite) Experience - 5+ Years Type - W2 Contract Job Description - Physical Design - Working with Cadence Flow, InnovGenus. Working on Block Level Implementation. Experience with Place and route, Floorplanning, Synthesis and timing Closure. Working on Blocks between 1-2 million instances. Experience at 2-7nm is ideal

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Full-time, Part-time, Contract, Third Party

Physical Design Engineer

California City, California

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3d ago

Job Title: Physical Design Engineer Employment Type: Full-Time (FTE) Locations: San Jose, CA / San Diego, CA / Irvine, CA Experience: 12+ Years Required Technical Skills Strong hands-on experience with Cadence Innovus. End-to-end Physical Design experience from RTL to tape-out. RTL synthesis and Static Timing Analysis (STA). Timing closure, including top-level STA. Place & Route (P&R), Clock Tree Synthesis (CTS), and clock-tree optimization. Floorplanning and physical layout. Physical veri

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Full-time

Depends on Experience

Physical Design Engineer

San Jose, California

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11d ago

Position: Physical design engineer Location: San Jose, CA(onsite) Job type: Contract JOB DESCRIPTION: Key Responsibilities Perform RTL synthesis, physical synthesis, floor planning, placement, clock tree synthesis (CTS), routing, and physical implementation. Drive timing closure, setup/hold optimization, and signal integrity improvements. Optimize power, performance, and area (PPA) across the physical design flow. Perform timing analysis, timing correlation, and constraint validation u

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Contract, Third Party

$70 - $100

Physical Design Engineer

San Jose, California

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3d ago

Role: Physical Design EngineerEmployment Type: Full-TimeLocations: San Jose, CA / San Diego, CA / Irvine, CAExperience: 12+ Years Key Responsibilities Execute end-to-end Physical Design, Synthesis, Physical Verification, and Timing Closure activities.Setup and synthesize RTL designs.Perform timing closure using various methodologies and strategies, including top-level STA.Conduct EM/IR analysis.Execute Place & Route (P&R).Develop and optimize Clock Tree Synthesis (CTS), including custom clock tr

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Full-time

Depends on Experience

Physical Design Engineer

Irvine, California

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3d ago

Locations:San Jose, CA / San Diego, CA / Irvine, CARequired Skills Strong experience withCadence Innovus.Expertise in the complete Physical Design cycle fromRTL to Tape-out.Hands-on experience in:SynthesisStatic Timing Analysis (STA)Timing ClosurePlace & RouteClock Tree Synthesis (CTS)FloorplanningPhysical VerificationEM/IR AnalysisStrongTCL and/or PERL scriptingskills.

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Full-time

Depends on Experience

Physical Design Engineer

Austin, Texas

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30+d ago

Job Description We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification. Optimize designs for Power, Performance, and Area (PPA) targets. Achieve timing clo

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Full-time

Depends on Experience

Physical Design Engineer

Sunnyvale, California

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2d ago

Role : Physical Design EngineerLocation- Sunnyvale, CA- OnsiteNeed a PDE with front end experience who is good with Synthesis, PDE flow and placement optimization.We are hiring an experienced Physical Design Engineer to join a high-performing silicon engineering team supporting one of the world's leading technology organizations in Sunnyvale, CA. This is an exciting opportunity to work on cutting-edge ASIC/SoC designs and collaborate with talented engineers throughout the chip development lifecy

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Third Party, Contract

Depends on Experience

Physical Design Engineer

Hybrid in Sunnyvale, California

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4d ago

We are hiring an experienced Physical Design Engineer to join a high-performing silicon engineering team supporting one of the world's leading technology organizations in Sunnyvale, CA. This is an exciting opportunity to work on cutting-edge ASIC/SoC designs and collaborate with talented engineers throughout the chip development lifecycle. Key Responsibilities Drive RTL synthesis and optimization to achieve performance, power, and area (PPA) goals Perform floorplanning for complex ASIC/SoC de

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Contract, Third Party

Depends on Experience

Physical Design Engineer

Palo Alto, California

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17d ago

Position: Physical Design Engineer Location : Palo Alto, CA (Full Onsite) Rate : 90-100/hr Client : HCL/Tesla Job ID : 166019 Number of Positions : 5 JD for PD: Exposure to TSMC 2NP/3NP is mustPerform endtoend physical design flow:FloorplanningPower planning (PG grid, IR)Placement & optimizationCTS (Clock Tree Synthesis)RoutingPostroute optimizationAchieve timing closure across all modes and cornersResolve DRC, LVS, ERC and signoff violationsHandle lowpower design techniques:MultiVt, Multivolta

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Contract

Depends on Experience

Physical Design Engineer – Lead

San Jose, California

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17d ago

Position: Physical Design Engineer Lead Locations: San Jose, San Diego, Irvine, CA (Onsite) What You Will Do: Drive ASIC physical design implementation from floorplanning through signoff. Perform Place & Route (PnR), Clock Tree Synthesis (CTS), timing closure, and optimization. Achieve Power, Performance, and Area (PPA) targets. Develop and validate timing constraints and perform Static Timing Analysis (STA). Execute LEC, VCLP, and EMIR signoff activities. Collaborate with cross-functional

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Full-time

Depends on Experience