JEDEC Jobs in California

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EEE Components Engineer

SpaceX

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Hawthorne, California, USA

Full-time

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. COMPONENTS ENGINEER The (electrical, electronic, and electro-mechanical/electro-optical) parts reliability team at SpaceX is a multidisciplinary group dedicated to ensuring the reliability of high-performance 38999
Posted 60+ days ago | Updated moments ago

Sr. Signal Integrity and Power Integrity Engineer

AMD (Advanced Micro Devices)

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Santa Clara, California, USA

Full-time

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellenc
Posted 27 days ago | Updated moments ago

SoC Architect, Memory Subsystem (Principal Engineer)

Samsung Electronics America

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San Jose, California, USA

Full-time

Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the wo
Posted 25 days ago | Updated moments ago

Principal Engineer - Silicon Validation Engineer

Marvell Semiconductor Inc.

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Santa Clara, California, USA

Full-time

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and be
Posted 47 days ago | Updated moments ago

Signal and Power Integrity Engineer (Multiple Locations)

Qualcomm Technologies

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San Diego, California, USA

Full-time

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (
Posted 60+ days ago | Updated moments ago

Validation Engineer with DDR Familiarity

Qualcomm Technologies

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San Diego, California, USA

Full-time

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. Qualcomm's Silicon Validation team is part of the central SoC digital hardware organization responsible for the overall quality of the SoC si
Posted 37 days ago | Updated moments ago

Engineer|6117 Engineer|6117

ACL Digital

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San Diego, California, USA

Full-time

Job Description: Top 5 Required Skills (These are not preferred skills. If the candidate does not have these required skills, they will be rejected completely) Familiarity with DDR interface, JEDEC spec, bus level view of transactions Regression and PVT testing Emulation Build Validation Potency in reading C code, understanding code flow, code manipulation, and test iteration. Technologies: C Programming Required Education: Bachelor's degree in Computer Science, Electrical/Electronics Engineeri
Posted 60+ days ago | Updated moments ago

Senior Reliability Engineer

NVIDIA Corporation

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Santa Clara, California, USA

Full-time

For two decades, NVIDIA has pioneered visual computing, the art and science of computer graphics. With our invention of the GPU - the engine of innovative visual computing - the field has expanded to encompass personal computer games, movie production, product design, artificial intelligence, medical diagnosis and scientific research. Today, visual computing is becoming increasingly central to how people interact with technology, and there has never been a more exciting time to join our team. NV
Posted 60+ days ago | Updated moments ago

PCB Layout designer

Ace Technologies, Inc.

•

Mountain View, California, USA

Third Party, Contract

Mt. View, CAClient is open to contract to hireMinimum 5 plus years, more experienced the better, onsite 3 days a weekLooking for 2 contractors (will want to convert)1 in Mtn View, CA 1 in bostonHybrid- 3 days onsite pick your own daysPCB layout of high-speed, high-density multi-layer printed circuit boards, 14-layers and upCreate a constraint-driven routing methodologyDevelop and maintain a corporate library of component footprintsInterface to outside PCB layout service bureaus when necessaryWor
Easy Apply
Posted 43 days ago | Updated 17 days ago

DV Engineers DDR (either IP or SoC level experience)- Remote

E-Solutions, Inc.

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California, USA

Full-time, Contract, Third Party

Role: DV Engineers DDR (either IP or SoC level experience) Work Location: USA (Remote) Experience: 10+ Years Key Responsibilities: Define and implement verification strategies and test plans for DDR memory interface designs. Develop UVM/SystemVerilog-based testbenches and reusable verification components. Perform protocol-level verification for DDR memory interfaces and validate compliance. Collaborate with architecture, RTL, and system teams to understand design intent and corner cases. Own f