Junior Physical Design Engineer jobs

Mountain View, California

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12d ago

We are looking for a Physical Design Engineer with hands-on experience in TSMC 3nm/2nm at SOC for cutting-edge GPU / High-Performance designs. Key Responsibilities: 1. Own Netlist-to-GDSII for high-speed, low-power SOC 2. Floorplanning, Placement, CTS, Routing, Timing closure 3. Drive PPA optimization - Power, Performance, Area for 2nm/3nm 4. Handle advanced nodes issues: IR Drop, EM, Crosstalk etc 5. Hands on experience on tools - Synopsys Fusion Compiler, Innovus, Primetime, Calibre Very Imp S

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Contract

$60 - $70

VLSI Physical Design Engineer - ASIC/SoC - RTL to GDS (10+ Yrs)

Folsom, California

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Today

VLSI Physical Design Engineer - ASIC/SoC - RTL to GDS Folsom, CA 3 + Months Role: Lead block-level physical design from RTL to GDSII. Must Have: 10+ years exp, advanced nodes, and Fusion Compiler. Dexian stands at the forefront of Talent + Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,000 professionals. As one of the largest technology and professional staffing companies and one of the largest minority-owned staffing companies in the Un

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Contract, Third Party

$90 - $100 per hour

Physical Design Engineer (Synthesis, STA & Floorplanning)

California

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Today

Fulltime Location: Bay Area Visa - Stamped H1B, s. Note: Stamped H1B engineers, who are currently in India and are willing to join us immediately can also be considered. Job Description Physical Design Engineer (Synthesis, STA & Floorplanning) Strong experience in RTL synthesis using Cadence Genus, including SDC constraint development and QoR optimization (timing, area, power) Hands-on expertise in Static Timing Analysis using Cadence Tempus, including setup/hold closure, C scenarios, OCV, an

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Full-time

physical design engineer

Mountain View, California

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Today

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Contract

Depends on Experience

Physical Design Engineer

Mountain View, California

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Today

Job Title: Physical Design Engineer Location: Mountain View, CA (Onsite) We are looking for a Physical Design Engineer with hands-on experience in TSMC 3nm/2nm at SOC for cutting-edge GPU / High-Performance designs. Key Responsibilities: 1. Own Netlist-to-GDSII for high-speed, low-power SOC 2. Floorplanning, Placement, CTS, Routing, Timing closure 3. Drive PPA optimization - Power, Performance, Area for 2nm/3nm 4. Handle advanced nodes issues: IR Drop, EM, Crosstalk etc 5. Hands on experience on

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Third Party, Contract

$60+

Physical Design Engineer

San Jose, California

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5d ago

Physical Design Engineer Location: San Jose CA- 5 Days onsite What will you do : * Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure * Setup and Synthesizing RTL * Timing closure through various methods and strategies; preferable in-depth experience in top-level STA * EM/IR Analysis, * Place and Route * Clock Tree Synthesis; experience with custom clock trees, insertion reduction and skew balancing techniques * Floor-planning and Layout; preferable in-depth exper

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Full-time

Up to $200,000

Physical Design Engineer || San Jose CA / Austin TX(Onsite)

San Jose, California

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Today

Role: Physical Design Engineer Location: San Jose CA / Austin TX (Onsite) Job description: We are seeking a Physical Design contractor with strong synthesis and implementation expertise to support large, timing-critical designs at advanced technology nodes. Qualifications: Proven experience with large-scale SoC or AI-class designs At least 5 years of PD experience Hands-on experience at advanced / cutting-edge technology nodes (e.g., N5, N3 or below) Strong understanding of timing closure a

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Contract, Third Party

$80

Physical Design Engineer

Palo Alto, California

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Yesterday

Employment Eligibility Statement: Due to specific project and client requirements, this position is open to U.S. Citizens and U.S. Lawful Permanent Residents (s). Sponsorship is not available at this time. Danta Technologies evaluates all candidates in compliance with the Immigration and Nationality Act (INA) and EEOC guidelines. All hiring decisions are made without regard to race, color, religion, sex, gender identity, sexual orientation, national origin, age, disability, veteran status, or an

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Contract

$78 - $80

Physical Design Engineer

Austin, Texas

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11d ago

Job Description We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification. Optimize designs for Power, Performance, and Area (PPA) targets. Achieve timing clo

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Full-time

Depends on Experience

Physical Design Engineer

San Jose, California

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13d ago

Job Title: Physical Design Engineer Location: San Jose CA Contract We are seeking a Physical Design contractor with strong synthesis and implementationexpertise to support large, timing-critical designs at advanced technology nodes. Key Responsibilities: Perform synthesis using Cadence Genus for large, timing-challenged designsDrive PPA (power, performance, area) optimization through synthesis and earlyimplementation stages. Develop and refine floorplans using Cadence InnovusCollaborate c

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Contract, Third Party

$60 - $80

Physical Design Engineer

Mountain View, California

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4d ago

Physical Design Engineer (PnR / PPA / Timing Closure) Mountain View CA / Austin TX Open to Both FTE and Contract Option Salary: Market We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floorplanning, power planning, placement, clock tree synthesis (CTS), ro

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Full-time, Third Party

Depends on Experience

Physical Design Engineer

San Francisco, California

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14d ago

Physical Design EngineerBay Area, CABelow is the Job Description:Good understanding of Cadence tools (Innovous, Quantus, Voltus).Deep knowledge about industry standards in Physical Design, Physical aware synthesis, Floorplanning, CTS and place and route.Experience in developing and implementing Power-grid and high speed clock constraints and specifications.Good understanding of physical design verification methodology to debug LVS/DRC issues at the chip and block level.Experience with CDC, stati

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Contract

65 - 75

ASIC Physical Design Engineer

Lafayette, Indiana

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5d ago

Were hiring for a full-time opportunitywith a leading semiconductor end client in Lafayette, IN. Seeking experienced ASIC Physical Design / Backend Engineers with strong TSMC FinFET tapeout and signoff experience.. Detailed job description is given below. Title:ASIC Physical Design Engineer (TSMC / FinFET) Location: Lafayette, Indiana (Relocation assistance provided) Type: Full time with Client Tapeout , Signoff , DRC/LVS/PEX,Customer interaction Job Responsibilities: Act as the primary inter

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Full-time, Third Party

Depends on Experience

Physical Design Engineer (Top-Level / Full-Chip) - AS

San Jose, California

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7d ago

Title: Physical Design Engineer/ ASIC Implementation Engineer (Strong Top-Level / Full-Chip Physical Design and Implementation experience) Location: San Jose, CA (Onsite role) Type: FTE Permanent role Note from Hiring manager: Candidate either should have good experience on Chip level/Top level design Or if they are extremely strong in one of the other aspects of design e.g. STA (Static Timing Analysis) or Floor Planning in chip design, they can still be considered. Only in those cases where y

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Full-time

Depends on Experience

Physical Design Engineer- senior

Austin, Texas

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Today

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what\'s possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (bloc

Full-time

Compensation information provided in the description

Physical Design Engineer II (IC)

San Jose, California

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Today

Position:Physical Design Engineer II (IC) Job Description:Job Responsibilities: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.Partner with the design team to proactively identify and

Full-time

Compensation information provided in the description

CPU Physical Design Engineer, San Diego

San Diego, California

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Today

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > CPU Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what\'s possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm CPU Engineer, you will lead innovative Central Processing Unit (CPU) design efforts that have a critical impact on industries across the world. Qualcomm Engine

Full-time

Compensation information provided in the description

Jr. Data Engineer

Los Angeles, California

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Today

Junior Data Engineer We are seeking a Junior Data Engineer to join a growing data team focused on building, maintaining, and optimizing data pipelines. This role offers a strong opportunity for professional growth through hands-on experience with modern data technologies, mentorship from experienced engineers, and direct exposure to business intelligence and analytics initiatives. The ideal candidate has 1 to 3 years of experience in data, analytics, or software engineering and is eager to deep

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Full-time

$105000 - $115000 per annum

Manager: Physical Design Engineer

Dallas, Texas

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14d ago

Ready to make a difference? We are seeking a Department Manager, Substation Physical Engineering to lead and grow our substation engineering practice. In this leadership role, you will be responsible for the operational management, technical oversight, staff development, financial performance, and strategic growth of a department delivering substation physical engineering services to utility clients nationwide. You will provide leadership to a multidisciplinary team of substation physical engin

Full-time

USD 174,701.00 - 296,992.00 per year

AI Silicon Physical Design Engineer

Sunnyvale, California

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Today

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. Cerebras works with the leading model labs, global enterprise

Full-time

USD 150,000.00 - 250,000.00 per year