LEC jobs in Santa Clara, CA

San Jose, California

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14d ago

Position: Physical Design Engineer Lead Locations: San Jose, San Diego, Irvine, CA (Onsite) What You Will Do: Drive ASIC physical design implementation from floorplanning through signoff. Perform Place & Route (PnR), Clock Tree Synthesis (CTS), timing closure, and optimization. Achieve Power, Performance, and Area (PPA) targets. Develop and validate timing constraints and perform Static Timing Analysis (STA). Execute LEC, VCLP, and EMIR signoff activities. Collaborate with cross-functional

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Full-time

Depends on Experience

Product Engineer II, Conformal

San Jose, California

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Today

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This opportunity is for a Product Engineer working with the Conformal Products. You will be part of a highly efficient and independently-minded team of engineering professionals focused on our top customer's success. You will also be working closely with R&D to help deliver new product features, enhancements, and solutions. Must be able to work with strict deadlines, provide systematic

Full-time

USD 105,000.00 - 195,000.00 per year

ASIC/FPGA Design and Verification Engineer - Space Electronics - MTV (Associate, Experienced, or Lead)

Mountain View, California

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Today

ASIC/FPGA Design and Verification Engineer - Space Electronics - MTV (Associate, Experienced, or Lead) Company: The Boeing Company Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC and/or FPGA Design and Verification Engineers to join us as part of our Boeing Electronic Products team at the heart of Boeing's products in Mountain View, CA. From complex digitally beamformed phased arrays for constellation satellite programs to computing and networking eq

Full-time

USD 98,600.00 - 133,400.00 per year

ASIC/FPGA Design and Verification Engineer - Space Electronics - (Senior or Principal) - MTV

Mountain View, California

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Today

ASIC/FPGA Design and Verification Engineer - Space Electronics - (Senior or Principal) - MTV Company: The Boeing Company Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC/FPGA Design and Verification Engineers (Senior or Principal) to join us as part of our Boeing Electronic Products team at the heart of Boeing's products; ASICs and FPGAs in Mountain View, CA. From complex digitally beamformed phased arrays for constellation satellite programs to comput

Full-time

USD 164,900.00 - 223,100.00 per year

Lead ASIC DFT Engineer

Remote

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Today

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues. The ideal candidate will have strong hands-on expertise in DFT fundamentals

Full-time

Asics Engineer

Remote

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Today

Requirements please see these key words of in the project description for the profile consideration. "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requir

Full-time

Lead ASIC DFT Staff Engineer

Remote

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8d ago

Required Skills & Qualifications: Strong hands-on experience in ASIC DFT with end-to-end ownership.Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.Experience with MBIST implementation and verific

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Third Party, Contract

90 - 100

Lead ASIC DFT Staff Engineer

Remote

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Today

Job Description: Key Skills : "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertio

Contract

USD70.0/HOURLY - USD80.0/HOURLY

CPU Synthesis CAD Engineer

Santa Clara, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency, and scalability. As a CPU Synthesis CAD engineer, you will build and support the world's best

Full-time

USD 209,300.00 - 313,900.00 per year

LEC jobs in Santa Clara, CA, USA