LEC Jobs in Washington

1 - 6 of 6 Jobs

Design Verification EngineerJob Title - Design Verification Engineer

TecHobbitCompany Name - TecHobbit

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Remote

Contract

Title: Design Verification Engineer Location: Remote Duration: 12 months with possible extension Requirement: Good Design Verification Skill with major GLS work experience. Expertise in testbench updates for GLS Expertise in Scripting languages perl or python Experience with Make, Yaml & Json file systems. Experience with 0 delay simulations and post layout simulations with SDF back annotations (Best/Typical/Worst Case analysis). Good understanding of RTL synthesis , Static Timing Analysis &

Design Verification Engineer|| RemoteJob Title - Design Verification Engineer|| Remote

Zodiac Solutions Inc.Company Name - Zodiac Solutions Inc.

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Contract, Third Party

Position : Design Verification Engineer Location: Remote Job Description : Good DV Skill with major GLS work experience. Expertise in testbench updates for GLS Expertise in Scripting languages perl or python Experience with Make, Yaml & Json file systems. Experience with 0 delay simulations and post layout simulations with SDF back annotations (Best/Typical/Worst Case analysis). Good understanding of RTL synthesis , Static Timing Analysis & LEC Flows. Experience with flow optimizations such as

ASIC and/or FPGA Design and Verification Engineer (Entry Level, Associate or Mid-Level)Job Title - ASIC and/or FPGA Design and Verification Engineer (Entry Level, Associate or Mid-Level)

Boeing CompanyCompany Name - Boeing Company

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Fairfax, Virginia, USA

Full-time

ASIC and/or FPGA Design and Verification Engineer (Entry Level, Associate or Mid-Level) Company: The Boeing Company Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC and/or FPGA Design and Verification Engineers (Entry Level, Associate or Mid-Level) to join us as part of our Boeing Electronic Products team at the heart of Boeing's products; ASICs and FPGAs in Fairfax, VA. From complex digitally beamformed phased arrays for constellation satellite progr

ASIC and/or FPGA Design & Verification Engineer (Lead, Senior or Principal)Job Title - ASIC and/or FPGA Design & Verification Engineer (Lead, Senior or Principal)

Boeing CompanyCompany Name - Boeing Company

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Fairfax, Virginia, USA

Full-time

ASIC and/or FPGA Design & Verification Engineer (Lead, Senior or Principal) Company: The Boeing Company Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC and/or FPGA Design and Verification Engineers (Lead, Senior or Principal) to join us as part of our Boeing Electronic Products team at the heart of Boeing's products; ASICs and FPGAs in Fairfax, VA. From complex digitally beamformed phased arrays for constellation satellite programs to computing and n

Hardware Design Engineering Intern/ Co-Op (Graduate | Fall 2025 | Hybrid)Job Title - Hardware Design Engineering Intern/ Co-Op (Graduate | Fall 2025 | Hybrid)

AMD (Advanced Micro Devices)Company Name - AMD (Advanced Micro Devices)

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Remote or Austin, Texas, USA

Full-time

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellen

Design Verification Engineer- Remote- USAJob Title - Design Verification Engineer- Remote- USA

Yochana IT SolutionsCompany Name - Yochana IT Solutions

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Contract, Third Party

Good DV Skill with major GLS work experience. Expertise in testbench updates for GLS Expertise in Scripting languages perl or python Experience with Make, Yaml & Json file systems. Experience with 0 delay simulations and post layout simulations with SDF back annotations (Best/Typical/Worst Case analysis). Good understanding of RTL synthesis , Static Timing Analysis & LEC Flows. Experience with flow optimizations such as Grey/Black-boxing techniques Good at communicating requirements/issues wit