Saint Paul, Minnesota
•
Today
Location: St. Paul, MN Salary: $130,000.00 USD Annually - $220,000.00 USD Annually Description: We are seeking a Junior - Principal ASIC Design Verification Engineer to provide technical leadership across advanced digital, mixed-signal, ASIC, SoC, and FPGA verification programs. This is a highly visible role for a seasoned verification professional who excels at defining verification strategy, building scalable methodologies, solving complex technical challenges, and mentoring engineering team
Contract
USD 130,000.00 - 220,000.00 per year