SERDES jobs in Fremont, CA

Signal Integrity Engineer - Serdes, Satellites (Starlink)

Palo Alto, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SIGNAL INTEGRITY ENGINEER - SERDES, SATELLITES (STARLINK) SpaceX is leveraging its experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the

Full-time

USD 115,000.00 - 155,000.00 per year

Sr. SI/PI Engineer - Serdes, Satellites (Starlink)

Palo Alto, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. SI/PI ENGINEER - SERDES, SATELLITES (STARLINK) SpaceX is leveraging its experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world'

Full-time

USD 115,000.00 - 155,000.00 per year

Sr. Signal Integrity Engineer - Serdes, Satellites (Starlink)

Palo Alto, California

•

Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. SIGNAL ENGINEER - SERDES, SATELLITES (STARLINK) SpaceX is leveraging its experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world

Full-time

USD 115,000.00 - 155,000.00 per year

Principal / Lead Engineer PCIe Gen5/Gen6 Controller, PHY & SerDes Integration

San Jose, California

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Today

Position :Principal / Lead Engineer PCIe Gen5/Gen6 Controller, PHY & SerDes Integration Location :San Jose, CA Experience :10+ years Job Summary We are seeking a highly experienced Principal/Lead Engineer to drive the architecture, development, integration, and delivery of PCIe Gen5/Gen6 subsystems for next-generation SoCs and chiplet-based products. The candidate will lead PCIe Controller, PHY and SerDes integration activities, contribute to Transaction Layer development, and work closely with

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Contract, Third Party

Depends on Experience

Firmware Engineer (SerDes / Optical)

San Jose, California

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Today

Firmware Engineer (SerDes / Optical) San Jose, CA 6 + Months $80-95/HR Role: Design firmware bridging high-speed electrical SerDes, silicon photonics, and optical subsystems. Must Have: 8-10 years firmware experience (C/C++), SerDes systems, and PCIe/I 802.3 specifications. Dexian stands at the forefront of Talent + Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,000 professionals. As one of the largest technology and professional staffing

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Contract

$80 - $95 per hour

Analog High-Speed I/O Design Engineer

Hybrid in San Jose, California

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3d ago

Position 1: Analog High-Speed I/O Design Engineer 4 Candidates Location: San Jose, CA Experience: 815 years ( not more than 15 years) Key Skills: Analog High-Speed I/O, SerDes, DDR, HCSL Target Profile: Hands-on experience in high-speed analog I/O circuit design and development.

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Contract

60 - 65

Signal Integrity Engineer //Mt. View, CA//(AV)

Mountain View, California

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3d ago

Hi, Hope youre doing well!! Please find the requirement below. If you find yourself comfortable with the requirement please reply back with your updated resume or call me back at ) Signal Integrity Engineer 3-months CTH Location:Mt. View, CA (must be in the Bay Areaonsite work required) LinkedIn Profile About This Role a Signal Integrity engineer to drive the next generation products from concept to development. You will be part of the Signal Integrity, Power Integrity and Packaging

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Contract, Third Party

Depends on Experience

Signal Integrity Engineer

Hybrid in Santa Clara, California

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Today

Signal Integrity They will take contractors onsite preferred or remote for 6 months. $105hrpayrateMAX They will take fulltime candidate at $250k + Ben SERDES is a very hard must for both the SI and packaging positions. Signal Integrity Engineer- Power Integrity experience is a plus. Experience with HFSS, ADS, PowerSI. Experience with SERDES interfaces such as PCIe, PAM4, USB. Experience with Characterization and Bring Up. Will be leading the simulations and debugging. Signal Integrity (SI): Mo

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Full-time

Depends on Experience

Analog Layout Engineer

Oakland, California

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Today

Analog Layout Engineer Bay Area,CA (onsite) Longterm Contract Position OverviewWe are looking for an experienced Analog Layout Engineer with 8+ years of industry experience in advanced semiconductor process technologies. The ideal candidate will have strong expertise in high-speed analog/mixed-signal layout and hands-on experience with advanced 2nm, 3nm, and 5nm process nodes.The role involves ownership of complex analog and mixed-signal layout blocks, working closely with circuit designers and

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Contract, Third Party

Depends on Experience

SERDES Firmware Engineer

San Jose, California

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Today

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we're looking for talent who feel the same: people who want to leave the planet better than they found it, those who don't shy away from humanity's challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing

Full-time

USD 164,290.00 per year

Principal Engineer, SerDes AMS Design and Architecture

San Jose, California

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Today

Principal Engineer, SerDes AMS Design and Architecture Location: San Jose, CA (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD, MediaTek and Intel and manufactured in partnership with the world's leading semiconduct

Full-time

USD 200,000.00 - 260,000.00 per year

SerDes Application Engineer

San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: SerDes Applications Engineer In June of 2025, Broadcom announced the Tomahawk 6 switch series of devices delivering a world's first 102.4 Terabits/sec of switching capacity in a single chip - doubling the bandwidth of any Ethernet switch available on

Full-time

USD 121,900.00 - 195,000.00 per year

Principal Engineer, SerDes Validation

San Jose, California

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Today

Principal Engineer, SerDes Validation Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-pa

Full-time

USD 180,000.00 - 230,000.00 per year

Principal SerDes Bring-up Validation Engineer

San Jose, California

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Today

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-t

Full-time

USD 185,000.00 - 240,000.00 per year

Staff Firmware/Software Engineer- Embedded SoC/Microcontroller/DSP/SERDES/AEC/Microled/ODSP/PHY/AI Connectivity

Santa Clara, California

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Today

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleetin

Full-time

USD 111,070.00 - 166,400.00 per year

Principal PHY SerDes Validation Engineer

Santa Clara, California

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Today

Full-time

USD 150,680.00 - 225,700.00 per year

Analog Layout Engineer

San Francisco, California

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19d ago

Analog Layout Engineer Bay Area, CA Long term Contract Exp : Minimum 8 years and above Skill : 2nm, 3nm and 5nm process and high speed layout Blocks : LDO ,ADC and SERDES Tools : Cadence ,Virtuoso XL

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Contract

60 - 70

Staff Engineer Digital Signal Processing

San Jose, California

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Today

#WeAreIn for jobs that impact everyone's life.Join the thinkers, builders, and problem-solvers behind tomorrow's technology. As a Staff Engineer Digital Signal Processing on our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life.Are you in? Your Role Key responsibilities in your new role Automotive Phys including Automotive Ethernet/SerDe

Full-time

USD 125,680.00 per year

ASIC Implementation Engineer PD

San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the Asic Products Division. This position involves working with the latest technology to continue driving next generation Artificial Intelligence and PCIe Switch Pro

Full-time

USD 121,900.00 - 195,000.00 per year

Senior SI/PI Engineer - AI and Compute Server Design

Fremont, California

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Today

@HYVE Solutions, missions to help customers, business partners, and employees achieve success through shared goals, strategies, resources and technology solutions. At Hyve Solutions, signal and power integrity are among the most critical disciplines in delivering reliable, high-bandwidth AI and compute servers. As next-generation platforms push PCIe Gen5/Gen6, CXL, NVLink, DDR5/DDR6, and 224G SerDes to their limits, disciplined SI/PI engineering is essential to first-pass success. This role foc

Full-time

USD 127,000.00 - 170,000.00 per year

SERDES jobs in Fremont, CA, USA