Synopsys jobs | Dice.com

Boise, Idaho

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Advanced Mask Development department in Micron?s Technology Development organization delivers reticle solutions that help shape next-gen memory and storage products in the evolving global tech

Full-time

Digital Failure Analysis Engineer (R&D)

Lehi, Utah

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Today

Job Description About the job: As an Electrical Failure Analysis (EFA) Engineer, you will perform various electrical investigative work on defect, performance and design-related issues during the technology development phase pertaining to a broad range of products in order to deliver qual-capable and high-yielding devices. This position also requires the ability to develop testing algorithms to successfully segment various electrical failures. You will also be adhering to all lab safety guidel

Full-time

Design Verification (DV) Engineer

Sunnyvale, California

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5d ago

About the role: The DVE is responsible for developing and verifying silicon IP. The DVE should have hands-on experience taking leading-edge digital silicon IP from idea to bring-up, working with Architecture/Micro-architecture, PD, and Software teams. This is an on-site role and will require presence in the office 5 days a week. No hybrid option is available. What you'll do: Develop, optimize, and verify digital silicon IP using an existing C or Python modelCreate and maintain specifications, b

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Contract, Third Party

Depends on Experience

ASIC Design Hardware Engineer - SDC/STA - San Jose, CA (Hybrid)

Hybrid in San Jose, California

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3d ago

ASIC Design Hardware Engineer - SDC/STA (Hybrid) Location: San Jose, California, United States of America You are a diligent Design / SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will develop timing constrains at both block level and fu

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Contract, Third Party

$70+

Clinical Scientific Director

Cambridge, Massachusetts

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Today

By clicking the ?Apply? button, I understand that my employment application process with Takeda will commence and that the information I provide in my application will be processed in line with Takeda?s and . I further attest that all information I submit in my employment application is true to the best of my knowledge. Job Description Are you looking for a patient-focused, innovation-driven company that will inspire you and empower you to shine? Join us as a Scientific Director in our NS Thera

Full-time

Compensation information provided in the description

Staff Physical Design Engineer

Sunnyvale, California

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5d ago

Required Qualifications: Bachelor s/Master s degree in Electrical Engineering or related field8 12 years of experience in ASIC physical designProven experience in full-chip or large block implementation and tapeoutsStrong expertise in:Floorplanning and power planningPlacement, CTS, routing, and physical verificationStatic Timing Analysis (STA) and timing closureHands-on experience with industry-standard tools such as: Synopsys ICC2 / Cadence InnovusSynopsys PrimeTimeMentor CalibreExperience with

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Contract, Third Party

Depends on Experience

FPGA Design/Verification Engineer

Owego, New York

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Today

Location: Owego, NY Salary: $70.00 USD Hourly - $80.00 USD Hourly Description: Role: Fpga Design/verification Engineer Location: (Hybrid) Employment type: contract Job Description: The selected candidate will be responsible for ASIC & FPGA development on R&D program. This engineer with have experience in developing, testing, and integrating digital signal processing (DSP), high speed digital design, high speed communication and system-on-chip (SOC) implemented on FPGA platforms. Experience

Contract

USD 70.00 - 80.00 per hour

CAD and PPA Methodology Engineer

San Diego, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: As a member of the Graphics team, the successful applicant will help develop new flows/methodologies and algorithms to improve power, performance and area (PPA) on state-of-the-art GPU cores while working closely with the graphics microarchitecture design and implementation teams. The successful candidate will possess basic understanding of RTL design and ASIC design

Full-time

USD 161,800.00 - 242,600.00 per year

Graphics ASICS Hardware Design Engineer

San Diego, California

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Yesterday

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: At Qualcomm, we believe in the power of technology. For decades, our innovations have transformed entire industries, improved billions of lives, and addressed many of society's biggest challenges. With the world becoming increasingly connected, we have a tremendous opportunity to shape a better future. As an R&D engine that has revolutionized the way people connect, ou

Full-time

USD 195,200.00 - 292,800.00 per year

Senior Emulation Engineer

San Francisco, California

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2d ago

Senior Emulation EngineerExperience: 8+ Years Location: Bay Area, CA Duration: Long Term Contract Key skills: palladium or veloce or zebu, timing closure, PCIe, usb Job DescriptionWe are looking for a Senior Emulation Engineer with strong experience in hardware emulation and SoC/ASIC verification. Required Skills8+ years of experience in Hardware Emulation / SoC VerificationHands-on experience with Cadence Palladium, Siemens Veloce, or Synopsys ZeBuStrong experience in emulation bring-up, debugg

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Contract, Third Party

Depends on Experience

Early Career - Full Stack Developer

Phoenix, Arizona

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Today

Program Overview: This comprehensive instructor-led program prepares early-career professionals for enterprise Java full-stack developer roles. The program builds foundational and practical skills across Java, Spring Boot, Apache Kafka, React, Oracle Database, OpenShift, and CI/CD automation. The focus is hands-on and job-ready, equipping participants to contribute effectively to Java delivery teams from day one. Program Structure: Over 6 weeks, you'll attend virtual informative lectures, colla

Full-time

USD 16.00 - 25.00 per hour

Remote (PST time zone preferred) -- Lead ASIC DFT Engineer

San Jose, California

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19d ago

Hello Professional, Good Afternoon Please find the job description give below, if interested please share me your most updated copy of resume. Role: Lead ASIC DFT Engineer Work Setup: Remote, PST time zone preferred Experience Required:10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep tec

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Third Party, Contract

Depends on Experience

PD Engineer

San Diego, California

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18d ago

We''re Hiring: Senior Physical Design (PD) Engineer Location: Bay Area, CA (Onsite) Experience: 8+ Years Sivaltech is looking for an experienced Senior Physical Design (PD) Engineer to join our semiconductor team. If you have expertise in advanced-node ASIC physical design and are passionate about delivering high-quality silicon, we''d love to connect with you! Key ResponsibilitiesPerform end-to-end ASIC physical design implementation from netlist to GDSII. Drive Floorplanning, Placement, Clock

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Full-time, Third Party

180,000 - 200,000

Physical Design Engineer (PD/PnR)

Austin, Texas

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30+d ago

Job Role -Physical Design Engineer (PD/PnR)Location- Bay Area CA / Austin TX (Hybrid) Job Summary Seeking a Physical Design Engineer with strong hands-on experience in block-level and top-level Place & Route using Synopsys Fusion Compiler. The candidate will be responsible for implementation, timing closure, low-power integration, and signoff activities for complex SoC designs. Key Responsibilities Perform block-level and top-level Physical Design implementation using Fusion Compiler.Drive flo

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Full-time

130,000 - 140,000

Senior MBIST Engineer

Remote

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12d ago

Business Title: Senior MBIST Engineer Location: California Job Type: Contract Note: Remote, must be working as per PST time zone Position Summary: We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and

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Contract, Third Party

Depends on Experience

Physical Design Engineer/ Signoff Engineer - CA/ TX - (JK)

Austin, Texas

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30+d ago

About the Role We are hiring Static Timing Analysis engineers to strengthen the timing signoff team supporting a leading SoC manufacturer on advanced-node designs. In this role you will own timing constraints, drive block- and full-chip timing closure across all modes and corners, and collaborate closely with the physical design, synthesis, and DFT teams to deliver clean, silicon-ready timing signoff. The ideal candidate has strong fundamentals in static timing analysis, hands-on experience with

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Contract

Depends on Experience

DRAM Device & Cell Technology Engineer

Boise, Idaho

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation

Full-time

Systems Engineer (Linux / AWS) EDA platform

Hybrid in Manor, Texas

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3d ago

We are seeking a Systems Engineer (Linux / AWS) for the EDA platform. Experience Experience around 8-15 years, medior level to senior level depending on the scope. Location Austin, TX Role Summary The Systems Engineer role is responsible for ensuring the stable, secure, and efficient operation of compute, storage, and network infrastructure of the EDA platform of one of our customers. This role focuses on daytoday operations, reliability, capacity, and incident response, working closely with

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Contract, Third Party

Depends on Experience

Senior DRAM Design Engineer

Boise, Idaho

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron?s DRAM Design Engineering Group (DDEG) is where innovation meets excellence. We are passionate about advancing memory and storage technologies through collaborative engineering and creative

Full-time

Hardware & Software Engineering Applications System Administrator

Richardson, Texas

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5d ago

Position Summary We are seeking a highly technical, execution-focused Hardware & Software Engineering Applications System Administrator to support a core engineering applications environment. The System Administrator is responsible for the direct operational and technical execution of daily installation, packaging, configuration, administration, and troubleshooting activities for specialized research and development application toolchains. The successful candidate will provide disciplined opera

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Contract

Depends on Experience