San Jose, California
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Today
Position: Design For Test Engineer (IC) Job Description: What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT workRTL checks for scan-insertion compatibility using Synopsys SpyglassScan-Insertion using Tessent TestKompressATPG pattern generation:Compressed and Uncompressed ModeTools: Mentor Tessent, Cadence Modus & Synopsys TetramaxPattern Simulation:Without timing, With timing for different cornersTools: VCSMismatch debug using VerdiScripting with Perl, Shell, T
Full-time
USD 95,900.00 - 170,500.00 per year
