Timing Closure jobs in Boxborough, MA

Boxborough, Massachusetts

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Today

Job Description Job Title: Hardware Design Engineer 2 Work Site Type: 100% Onsite- Boxborough, MA Contract Term: 12 Months Contract Description: THE ROLE: The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs a

Full-time

Lead FPGA Design Engineer

Bedford, Massachusetts

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Today

At MITRE, your passion fuels work that impacts our nation and improves lives. This is where your skills strengthen national security, cybersecurity, health, transportation, and citizen services. We're a nonprofit engineering, applied research, and advanced technology organization working in the public interest. With objectivity and integrity at our core, we lead federally funded research and development centers for U.S. government agencies - collaborating with industry and academia to deliver in

Full-time

USD 156,400.00 - 195,500.00 per year

FPGA Design Engineer

Nashua, New Hampshire

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Today

Company Description Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. What sets us apart is our relentless pursuit of innovation. We leverage the latest advancements in cloud computing, artificial intelligence, and software-defined networking to provide our clients with a competitive edge in an increasingly interconnected world. Our solutions are designed to not only meet the current demands of the digital la

Full-time

Principal Electrical Engineer - FPGA Design

Tewksbury, Massachusetts

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Today

Job DescriptionDate Posted: 2026-09-29\nCountry: United States of America \nLocation: US-MA-TEWKSBURY-TB1 ~ 50 Apple Hill Dr ~ ASSABET BLDG \nPosition Role Type: Onsite \nU.S. Citizen, U.S. Person, or Immigration Status Requirements: The ability to obtain and maintain a U.S. government issued security clearance is required. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance \nSecurity Clearance Type: DoD Clearance: Secret \nSecurity Clearance Status: Ac

Full-time

FPGA/ Digital Design Engineer I - Onsite

Marlborough, Massachusetts

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Today

Job DescriptionDate Posted: 2026-10-05\nCountry: United States of America \nLocation: US-MA-MARLBOROUGH-MA1 ~ 1001 Boston Post Rd ~ BLDG 1 \nPosition Role Type: Onsite \nU.S. Citizen, U.S. Person, or Immigration Status Requirements: Active and transferable U.S. government issued security clearance is required prior to start date. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance \nSecurity Clearance Type: DoD Clearance: Secret \nSecurity Clearance Stat

Full-time

FPGA/ Digital Design Engineer II - Onsite

Marlborough, Massachusetts

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Today

Full-time

Principal Engineer-Digital Signal Processing FPGA Designer

Tewksbury, Massachusetts

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Today

Job DescriptionDate Posted: 2026-09-15\nCountry: United States of America \nLocation: US-MA-TEWKSBURY-TB1 ~ 50 Apple Hill Dr ~ ASSABET BLDG \nPosition Role Type: Onsite \nU.S. Citizen, U.S. Person, or Immigration Status Requirements: Active and transferable U.S. government issued security clearance is required prior to start date. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance \nSecurity Clearance Type: DoD Clearance: Secret \nSecurity Clearance Sta

Full-time

Lead Firmware Engineer

Woburn, Massachusetts

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Today

System Development Division (SDD) is focused on delivering National Defense capabilities by driving mission-focused strategies to develop advanced technology systems enabling enduring products and solutions focused on achieving the customer vision. Our programs deliver sustainable, reliable, and cost-efficient capabilities focused on end-customer needs that function in operationally relevant environments and timeframes. SDD considers the entire lifecycle of the solution, from conceptualization a

Full-time

USD 173,000.00 - 238,000.00 per year

FPGA/ Digital Design Engineer I - Onsite

Tewksbury, Massachusetts

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Today

Job DescriptionDate Posted: 2026-10-05\nCountry: United States of America \nLocation: US-MA-TEWKSBURY-TB4 ~ 836 North St ~ INNOVATION BLDG \nPosition Role Type: Onsite \nU.S. Citizen, U.S. Person, or Immigration Status Requirements: Active and transferable U.S. government issued security clearance is required prior to start date. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance \nSecurity Clearance Type: DoD Clearance: Secret \nSecurity Clearance Stat

Full-time

ASIC/FPGA Methodology Engineer (TERADYNE, North Reading, MA)

Reading, Massachusetts

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Today

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world! We

Full-time

USD 154,900.00 - 247,800.00 per year

Physical Design Engineer GPU / High-Performance SoC

Remote

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Today

Job Title: Physical Design Engineer GPU / High-Performance SoC Location: Mountain View, CA (Full Onsite) Openings: 2 Job Description We are looking for an experienced Physical Design Engineer with hands-on experience in advanced semiconductor process nodes, particularly TSMC 3nm and/or 2nm, for high-performance SoC, GPU, or similar complex chip designs. The ideal candidate will have strong end-to-end physical design experience, from netlist to GDSII, along with expertise in PPA optimization, tim

Easy Apply

Contract

$60 - $80

Senior Principal Engineer

Remote or San Jose, California

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Today

Job Details: Job Description: Altera is looking for a Senior Principal Engineer to serve as a key technical leader responsible for defining and advancing FPGA physical synthesis, timing optimization, and implementation methodologies. This individual will bring deep expertise in EDA algorithms, optimization engines, design compilation, and performance-driven implementation technologies. The ideal candidate will have a proven track record of architecting and delivering breakthrough technologies

Full-time

USD 231,500.00 - 304,500.00 per year

Asics Engineer

Remote

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Today

Requirements please see these key words of in the project description for the profile consideration. "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requir

Full-time

Physical Design Engineer

Remote

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Today

Job Title: Physical Design Engineer Location: Remote We are looking for a Physical Design Engineer with hands-on experience in TSMC 3nm/2nm at SOC for cutting-edge GPU / High-Performance designs. Key Responsibilities: 1. Own Netlist-to-GDSII for high-speed, low-power SOC 2. Floorplanning, Placement, CTS, Routing, Timing closure 3. Drive PPA optimization - Power, Performance, Area for 2nm/3nm 4. Handle advanced nodes issues: IR Drop, EM, Crosstalk etc 5. Hands on experience on tools - Synopsys F

Easy Apply

Contract, Third Party

$60+

Lead ASIC DFT Staff Engineer

Remote

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9d ago

Required Skills & Qualifications: Strong hands-on experience in ASIC DFT with end-to-end ownership.Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.Experience with MBIST implementation and verific

Easy Apply

Third Party, Contract

90 - 100

Senior Engineer, Digital Design (Physical)

Wilmington, Massachusetts

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Today

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's inno

Full-time

USD 116,960.00 - 160,820.00 per year

Lead ASIC DFT Staff Engineer

Remote

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Today

Job Description: Key Skills : "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertio

Contract

USD70.0/HOURLY - USD80.0/HOURLY

Sr. FPGA Engineer

Marlborough, Massachusetts

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Today

IPG Photonics is revolutionizing the laser industry as the pioneering developer and leading producer of fiber lasers and amplifiers. Headquartered in Marlborough, MA, IPG has over 4,800 employees in more than 30 locations around the world. We aspire to work together with our employees and customers to apply light in ways that improve life. Our mission is to develop innovative laser solutions to make the world a better place. To accomplish this mission, we are committed to attracting and retainin

Full-time

Senior FPGA or ASIC Engineer

Bedford, Massachusetts

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Today

Full-time

USD 126,800.00 - 158,500.00 per year

Senior Staff GPU Physical Design Engineer

Remote

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Today

Job Description Title: Senior Staff GPU Physical Design Engineer Location: Austin, TX or San Jose, CA. onsite strongly preferred Need: GPU or high-performance SoC experience. Advanced node (?5nm). Full block ownership Position Summary We are seeking a Senior Staff GPU Physical Design Engineer for our client to work on the physical implementation of high-performance GPU and system-level IP, driving execution across synthesis, place-and-route, timing closure, and signoff for their advanced tech

Contract

Timing Closure jobs in Boxborough, MA 01719, USA