Timing Closure jobs in Remote

California

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Today

Our Mission At Palo Alto Networks , we're united by a shared mission-to protect our digital way of life. We thrive at the intersection of innovation and impact, solving real-world problems with cutting-edge technology and bold thinking. Here, everyone has a voice, and every idea counts. If you're ready to do the most meaningful work of your career alongside people who are just as passionate as you are, you're in the right place. Who We Are In order to be the cybersecurity partner of choice, w

Full-time

USD 173,600.00 - 280,700.00 per year

FPGA Engineer

Tewksbury, Massachusetts

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Today

FishEye Software is seeking an experienced FPGA Design Engineer to support the development of FPGA-based solutions for control and/or signal processing radar applications. In this role, you will collaborate with a cross-functional engineering team to architect, implement, and verify complex FPGA designs that meet demanding system requirements. This position requires eligibility to obtain a DoD Secret Security Clearance and is based on-site in Tewksbury, MA. Key Responsibilities: Design, develop,

Full-time

USD 80,000.00 - 190,000.00 per year

Digital Engineer 3

San Diego, California

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Today

Job#: 3041363 Job Description: Digital Engineer 3 Location: San Diego, California (Onsite) Clearance: Secret Clearance Role Overview Our organization is seeking a Digital Engineer for an on-site position. This role involves the design, development, integration, and testing of VHDL-based digital designs, with a primary focus on software-defined radio VHDL firmware codebases. The position is contingent upon program acceptance. Key Responsibilities Design, develop, integrate, and test VHDL-ba

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Full-time

$90 - $138 per hour

Senior Hardware/ Software Design Engineer

Maryland

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Today

Residency All applicants must currently reside in the United States Overview BigBear.ai is seeking an experienced senior HW/SW Design Engineer to join a small team to design, develop, construct, and test electronic hardware (FPGA) and software processing components for subsystems supporting RF communication and collection systems. This position requires expertise in FPGA development, digital signal processing implementation, and software-hardware integration to support mission critical require

Full-time

Digital Engineer 3

Los Angeles, California

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Today

Job#: 3043260 Job Description: Digital Engineer 3 Location: Woodland Hills, California (Onsite) Clearance: Secret Clearance Role Overview We are seeking a Digital Engineer for a role based in Woodland Hills, CA. The successful candidate will have an opportunity to be part of an enterprise-wide digital transformation. This position requires a collaborative, open, and team-oriented individual with a focus on team empowerment, shared responsibility, flexibility, continuous learning, and a cult

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Full-time

$65 - $87 per hour

Physical Design Engineer

Mountain View, California

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4d ago

Hi, Job Title: Physical Design Engineer (PnR / PPA / Timing Closure) Location : Mountain View, CA Responsibilities: We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Preferred Qualifications: Bachelor's or Master's degree in Electrical/Electronics Engineering.Experience in advanced nodes (7nm/5nm/3nm preferred).Strong debugging and problem-solving skills.Exp

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Full-time, Third Party

Depends on Experience

FPGA Firmware Engineer

Westminster, Colorado

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Today

Location: Westminster, CO Salary: $140,000.00 USD Annually - $155,000.00 USD Annually Description: FPGA Firmware Engineer Location: Westminster, CO Job Type: Full-Time Job Summary We are seeking an experienced FPGA Firmware Engineer to lead the design, development, and verification of FPGA-based digital systems and embedded firmware supporting advanced electro-optical, infrared, and high-performance sensing technologies. This role is responsible for FPGA logic design, embedded firmware devel

Contract

USD 140,000.00 - 155,000.00 per year

Elect Design and Analy Engr 5

El Segundo, California

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Today

Location: El Segundo, CA Salary: $110.00 USD Hourly - $112.00 USD Hourly Description: Our client is currently seeking a Elect Design and Analy Engr 5 which need active secret clearance Job Code: Elect Design and Analy Engr 5 Work Location: El Segundo, CA Shifts: 1st shift: 8:00 AM - 4:30 PM NEED ACTIVE SECRET CLEARANCE TO START WITH Job Description: The contractor will inherit FPGA top-level design and be responsible for creating and adding new functional blocks and interfaces, including in

Contract

Compensation information provided in the description

Digital Engineer (FPGA/ ASIC)

Los Angeles, California

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Today

Location: Los Angeles, CA Salary: $70.00 USD Hourly - $95.00 USD Hourly Description: Job Title: Digital Engineer (FPGA/ ASIC) Duration: 1+ year (Possible extension or Perm) Location: About the Role We are looking for you to join our team as a Principal Digital Engineer based out of Woodland Hills, CA. As a Principal Digital Engineer you will have a challenging and rewarding opportunity to be a part of our Enterprise-wide digital transformation. Using Model-based Engineering, DevSecOps and Agil

Contract

Compensation information provided in the description

ASIC Design Engineer

No location provided

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Today

JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and internal IP's. Successful candidates will be responsible for leading, and participating in, the design of leading edge SoC's in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-a

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Full-time, Contract, Third Party

ASIC/RTL Design Engineer

San Jose, California

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10d ago

Job Description: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and internal IPs. Successful candidates will be responsible for leading, and participating in, the design of leading edge SoC?s in advanced digital CMOS processes.Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro

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Third Party, Contract

Depends on Experience

Physical Design Engineer & DV Engineers

Sunnyvale, California

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20d ago

Job Title:PhysicalDesignEngineer(PD/PnR) Location Bay Area CA / Austin TX (Hybrid) Job Summary Seeking aPhysicalDesignEngineerwith strong hands-on experience in block-level and top-level Place & Route using Synopsys Fusion Compiler. The candidate will be responsible for implementation, timing closure, low-power integration, and signoff activities for complex SoCdesigns. Key Responsibilities Perform block-level and top-levelPhysicalDesignimplementation using Fusion Compiler. Drive floorplannin

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Full-time

160,000 - 170,000

Physical Design Engineer/ Signoff Engineer - CA/ TX - (JK)

Austin, Texas

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30+d ago

About the Role We are hiring Static Timing Analysis engineers to strengthen the timing signoff team supporting a leading SoC manufacturer on advanced-node designs. In this role you will own timing constraints, drive block- and full-chip timing closure across all modes and corners, and collaborate closely with the physical design, synthesis, and DFT teams to deliver clean, silicon-ready timing signoff. The ideal candidate has strong fundamentals in static timing analysis, hands-on experience with

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Contract

Depends on Experience

SoC Timing (Static Timing Analysis/STA) Engineer, HBM

Richardson, Texas

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron\'s Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern

Full-time

System FPGA Engineer

Remote or Utah

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: Job Description Our Mission We are dedicated to transforming the industry by reimagining silicon and developing next-generation computing platforms. By joining our team, you'll collaborate with world-class engineers to create innovative solutions that push the limits of performance, energy efficiency, and scalability. Our focus is on developing reference platforms based

Full-time

USD 146,400.00 - 219,600.00 per year

Senior Principal ASIC FPGA Engineer

Remote or Boise, Idaho

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Today

Basic Qualifications Education Requirements: Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 10 years of relevant experience; or Master's degree plus a minimum of 8 years of relevant experience. Clearance Requirements: Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eli

Full-time

USD 191,146.00 - 212,053.00 per year

STA Engineer

Fort Collins, Colorado

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom's ASIC Products Division (APD) in Fort Collins, Colorado, is looking for an experienced STA Engineer. As part of APD, you'll help design and manufacture next-generation, high-performance, power-efficient ASICs. In this role, you will be respon

Full-time

USD 129,400.00 - 207,000.00 per year

Staff STA Engineer

Austin, Texas

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Today

Arm has formed a new group to develop outstanding silicon demonstrators based on Arm's IP compute sub-system solutions and addressing markets such as premium mobile, infrastructure and automotive. Using innovative nodes such as 3nm and advanced SoC 2.5D and 3D technology, Arm strives to demonstrate powerful industry performance by crafting, developing, realizing, and producing modern silicon chips. Responsibilites: Owning full chip and block level timing closure throughout the entire project c

Full-time

USD 198,100.00 - 268,000.00 per year

388 Senior Hardware/Software Design Engineer

Annapolis, Maryland

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Today

About ARSIEM Corporation At ARSIEM Corporation we are committed to fostering a proven and trusted partnership with our government clients. We provide support to multiple agencies across the United States Government. ARSIEM has an experienced workforce of qualified professionals committed to providing the best possible support. As demand increases, ARSIEM continues to provide reliable and cutting-edge technical solutions at the best value to our clients. That means a career packed with opportun

Full-time

USD 167,000.00 - 187,000.00 per year

Asics Engineer

Remote

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Today

Requirements please see these key words of in the project description for the profile consideration. "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requir

Full-time