Timing Closure jobs in Washington

Physical Design Engineer GPU / High-Performance SoC

Remote

•

Today

Job Title: Physical Design Engineer GPU / High-Performance SoC Location: Mountain View, CA (Full Onsite) Openings: 2 Job Description We are looking for an experienced Physical Design Engineer with hands-on experience in advanced semiconductor process nodes, particularly TSMC 3nm and/or 2nm, for high-performance SoC, GPU, or similar complex chip designs. The ideal candidate will have strong end-to-end physical design experience, from netlist to GDSII, along with expertise in PPA optimization, tim

Easy Apply

Contract

$60 - $80

Physical Design Engineer

Remote

•

Today

Job Title: Physical Design Engineer Location: Remote We are looking for a Physical Design Engineer with hands-on experience in TSMC 3nm/2nm at SOC for cutting-edge GPU / High-Performance designs. Key Responsibilities: 1. Own Netlist-to-GDSII for high-speed, low-power SOC 2. Floorplanning, Placement, CTS, Routing, Timing closure 3. Drive PPA optimization - Power, Performance, Area for 2nm/3nm 4. Handle advanced nodes issues: IR Drop, EM, Crosstalk etc 5. Hands on experience on tools - Synopsys F

Easy Apply

Contract, Third Party

$60+

Senior Principal Engineer

Remote or San Jose, California

•

Today

Job Details: Job Description: Altera is looking for a Senior Principal Engineer to serve as a key technical leader responsible for defining and advancing FPGA physical synthesis, timing optimization, and implementation methodologies. This individual will bring deep expertise in EDA algorithms, optimization engines, design compilation, and performance-driven implementation technologies. The ideal candidate will have a proven track record of architecting and delivering breakthrough technologies

Full-time

USD 231,500.00 - 304,500.00 per year

Senior Hardware Engineer

Redmond, Washington

•

Today

Overview Microsoft Azure is building the fastest network in public cloud. We are seeking candidates who can span the stack from hardware to systems to applications, turning ideas into production systems at a rapid pace. Join us as a Hardware Engineer to build the world's fastest public cloud and make a difference to millions of people across the planet. As a developer in the Accelnet hardware team, you will be responsible for building, testing, and deploying networking acceleration on Azure --

Full-time

USD 119,800.00 - 234,700.00 per year

Senior FPGA/Silicon Design Engineer

Redmond, Washington

•

Today

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and complian

Full-time

USD 119,800.00 - 234,700.00 per year

Quantum Systems Digital Design Engineer II

Redmond, Washington

•

Today

Overview Microsoft is the world's center of expertise on topological quantum computing. We are building a scaled, fault-tolerant quantum computer grounded in topological qubits and integrated end-to-end with the Azure Quantum software stack. As a Quantum Systems Digital Design Engineer II, you'll collaborate closely with quantum physicists, systems software, RF/EE, and manufacturing/production to define, design, and deliver FPGA-based, ultra-low-latency digital subsystems that sit at the heart

Full-time

USD 102,100.00 - 202,200.00 per year

Staff Engineer, FPGA Design (R5347)

Washington

•

Today

Shield AI is a venture-backed defense-tech company with the mission of protecting service members and civilians with intelligent systems. Its products include Hivemind autonomy software, V-BAT and X-BAT aircraft, and Aechelon simulation and synthetic reality technologies. With offices and facilities across the U.S., Europe, the Middle East, and Asia-Pacific, Shield AI's technology actively supports operations worldwide. For more information, visit Follow Shield AI on LinkedIn, X, Instagram, and

Full-time

USD 180,000.00 - 280,000.00 per year

Asics Engineer

Remote

•

Today

Requirements please see these key words of in the project description for the profile consideration. "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requir

Full-time

Senior FPGA Engineer

Bellevue, Washington

•

7d ago

Senior FPGA Engineer Bellevue, WA - Relocation Assistance Provided The Company Our client is a global leader in aviation technology, specializing in cabin systems integration for business and commercial aircraft. They design their audio, video, lighting, and entertainment systems completely in-house, from concept through production and support. The Job Our client is looking for a Senior FPGA Engineer to join their team in an onsite role. The position requires strong technical expertise in X

Full-time

Lead ASIC DFT Staff Engineer

Remote

•

9d ago

Required Skills & Qualifications: Strong hands-on experience in ASIC DFT with end-to-end ownership.Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.Experience with MBIST implementation and verific

Easy Apply

Third Party, Contract

90 - 100

Lead ASIC DFT Staff Engineer

Remote

•

Today

Job Description: Key Skills : "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertio

Contract

USD70.0/HOURLY - USD80.0/HOURLY

Senior Staff GPU Physical Design Engineer

Remote

•

Today

Job Description Title: Senior Staff GPU Physical Design Engineer Location: Austin, TX or San Jose, CA. onsite strongly preferred Need: GPU or high-performance SoC experience. Advanced node (?5nm). Full block ownership Position Summary We are seeking a Senior Staff GPU Physical Design Engineer for our client to work on the physical implementation of high-performance GPU and system-level IP, driving execution across synthesis, place-and-route, timing closure, and signoff for their advanced tech

Contract

Timing Closure jobs in Washington, USA