Verilog jobs

Expert level verification engineer with strong SystemVerilog and UVM experience. As an alternative to SystemVerilog/UVM, we are open to candidates with a verification background in lab testing and/or design verification testing. Experience with design on Xilinx products would be a strong plus. Required Skills: Expert level verification engineer with strong SystemVerilog and/ or UVM experience orFPGA verification in lab testing and/or Hardware FPGA design verification testingExperience with desi