Verilog jobs | Dice.com

Sunset Valley, Texas

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18d ago

Job Description:Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence)Strong proficiency in System Verilog Assertions (SVA) and formal property specificationExperience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysisFamiliarity with scripting languages (TCL, Python, Perl) for flow automationExtensive experience in design verification with a strong focus on formal verificationExpertise in Syst

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Contract, Third Party

Depends on Experience

Formal Verification

Ben Lomond, California

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13d ago

JOB DUTIES: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run du

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Third Party, Contract

Depends on Experience

Verification Engineer in CA and TX

San Francisco, California

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28d ago

Hi, I hope all is well. I am doing a search for a client who has an urgent requirement for a network administrator contract opportunity. The job description is listed below. If this is something you are interested in, please call me ASAP at . please mail me your updated resume in Word format, availability, contact details, and hourly rate as per the hiring policy of our client. ASIC Verification Engineer About the role: PCIe Protocol IP Verification Expert: Consulting & Turnkey projec

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Third Party, Contract

Depends on Experience

Verification Engineer

Hybrid in Santa Clara, California

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27d ago

Role: Verification Engineer Location: Santa Clara, CA & Contract Job Description: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Be responsible for carefully documenting and executing test p

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Contract

Depends on Experience

Hardware Design Engineer

Hillsboro, Oregon

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Today

Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional HW Design Engineer to join our MCG team in Hillsboro. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per w

Full-time

USD 106,900.00 - 198,500.00 per year

DFT Engineer

California

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Today

Job Title: DFT Engineer Location: Saratoga, CA (Onsite) Duration: Contract & Full-Time Job Description: Define the DFT architecture of a multi-chip system SOC. involving all aspects of test design functions such as Scan, BIST, Memory Repair, BSD ( ACJTAG/DCJTAG). Proficiency in Synthesis design constraints. ( Ie SDC) Prior experience with Serializers/Deserilizers. Sound Proficiency in either Mentor /Synopsys Test Tools required. Proficiency is synthesis, Define and implement OCC. Exposure to

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Full-time

Field Programmable Gate Array

Ben Lomond, California

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6d ago

Job Description: This role is an exciting opportunity in SBIO team to create FPGA hardware validation platforms and debugging complex issues involving both hardware and software. Collaborate with design and firmware teams to define validation plans and execute on FPGA prototyping platforms. This role requires a proven track record of successfully bringing complex FPGA designs from concept through production quality, with strong debugging and problem-solving capabilities. The PersonStrong analyt

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Contract, Third Party

Depends on Experience

DFT Engineer

Santa Clara, California

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26d ago

Job Title: DFT Engineer Location: Santa Clara, CA Work Arrangement: Onsite Experience: 5+ Years JOB DESCRIPTION We are seeking an experienced DFT Engineer to join a cutting-edge Silicon Engineering team working on next-generation GPU and AI products. The ideal candidate will have strong expertise in Design for Test (DFT) architecture, scan, MBIST, LBIST, JTAG, ATPG, and silicon debug. This is an excellent opportunity for a hands-on DFT Engineer to contribute to complex ASIC/SoC designs and next-

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Contract, Third Party

80 - 100

RTL Engineer, Networking ASIC

Saratoga, California

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26d ago

Qualifications ME/BE with a minimum of 8-15 years of experience.Hands-on knowledge of SystemVerilog and Verilog is mandatory.Solid understanding of ASIC design methodologies, including simulation, verification, synthesis, and timing adjustments.Proven expertise in designing and optimizing scheduling and QoS mechanisms.Experience with Ethernet and IP protocols.Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking i

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Full-time

200000 - 220000

DFT MBIST Staff Engineer

Remote

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4d ago

Position Summary: We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and Silicon bring-up with minimal supervision. Responsibilities: Perform MBIST insertion for complex SoC designs using Synopsys SMS

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Contract, Third Party

Depends on Experience

Design Engineer II # 26-23167

Remote

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7d ago

Duration: 8 Months Contract Summary: Overview Contract digital design engineer to integrate the lowspeed peripheral subsystem I3C, I2C, SPI/QSPI/OSPI, UART controllers including the IO cells, pad ring connectivity and IO multiplexing that these peripherals depend on. Duties Integrate I3C, I2C, SPI/QSPI/OSPI and UART controller IPs into the peripheral subsystem and SoC top Own IOlevel integration: pad/IO cell selection and configuration, IO mux design and programmability, pullup/pulldown, drive

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Contract

$70 - $150

Mixed Signal Verification Engineer

San Jose, California

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18d ago

Job Responsibilities: Creating AMS/DMS testbench for wireless RF and High Speed PHY.Working with RF/Analog design engineers for analog circuit modelsSupport silicon bring-up and commercialization. Required Skills: BS or BE minimum, 3+ year experiences Deep understanding of digital VLSI simulation flow Deep understanding of mixed-mode and analog simulation flow Experience with Verilog/SystemVerilog and RNM modeling Experience with digital verification, UVM, and waveform debug Teamwork, dedication

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Contract

94 - 155

Senior FPGA Engineer

Chandler, Arizona

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20d ago

Senior FPGA Engineer Location: Chandler, AZ (Onsite 5 days/week) Position SummaryWe are seeking a Senior FPGA Engineer with experience across the entire design flow for complex FPGAs to lead the design, development, and debugging of FPGA SoC systems supporting advanced satellite communications technologies. This role focuses on advanced IP integration, high-performance RTL development, and userspace driver/firmware development. ResponsibilitiesDesign, develop, document, debug, and test FPGA SoC

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Full-time

$120000 - $150000

Design Engineer II # 26-23166

Remote

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7d ago

Duration: 8 Months Contract Summary: A contract digital design engineer to own integration of the camera ingest path MIPI C/DPHY and CSI2 receivers into the image signal processing (ISP) pipeline including development of the glue logic required to bridge CSI2 and ISP interfaces. Duties:Integrate MIPI CPHY/DPHY, CSI2 controller and ISP IPs at subsystem and chip levelDesign and code the glue logic between CSI2 output and ISP input: stream/virtualchannel handling, datatype unpacking, line/frame

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Contract

$70 - $150

DFT Engineer Intern

No location provided

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Today

AI Vision Processors For Edge Applications Our solutions make cameras smarter by extracting valuable data from high-resolution video streams. Job Description Position Responsibilities: Logic Design to support DFT featuresAutomate DFT Flows (Scan, Compression & MBIST) used for complex multi-million gate SoCVerification of DFT Logic and analysis of fault coverageTiming analysis for DFT Modes Minimum Requirements: MSEE in Electrical / Computer EngineeringKnowledge of DFT fundamentalsKnowledge of

Full-time

FPGA Engineer

Melbourne, Florida

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Today

Required Skills: Expert-level verification engineer with strong SystemVerilog and/ or UVM experience orFPGA verification in lab testing and/or Hardware FPGA design verification testingExperience with design on Xilinx products would be a strong plusexpected to communicate effectively with emerging engineers at the India GETC-I site and provide both technical and process (DO-254) guidance to the verification team. Core Responsibilities RTL Design & Simulation: Develop code and testbenches using VH

Full-time

ASIC Design Engineer

Mountain View, California

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Today

Hi , This role is a Full Time / Permanent . Title: Senior ASIC / SoC Network-on-Chip Design Engineer or Senior ASIC Design Engineer Location : Mountain View CA Qualifications 8+ years delivering ASIC/SoC IP designs. 6+ years of hands-on digital design, RTL, and microarchitecture experience. Strong experience with Verilog/SystemVerilog, synthesis, timing constraints, CDC, Lint, and PPA trade-offs. Experience with NoC/interconnect and high-throughput/low-latency designs. Experience with SoC

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Full-time

Depends on Experience

Systems Engineer

Austin, Texas

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6d ago

Job Description: The needs of this role require the candidate to have an in-depth understanding of microprocessor product development, as well as being able to solve multiple concurrent complex problems on aggressive timelines. The candidate must have excellent collaboration and communication skills. The candidate must have a proven track record of working well across teams and delivering projects to completion Key Responsibilities: Directed focus on the goals of improving product time-to-market

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Contract, Third Party

Depends on Experience

RTL Engineer

Washington

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Today

As a RTL Engineer, a typical day might include the following: Invents, analyzes and designs complex analog and digital circuits to meet specifications. Lead hardware design reviews to demonstrate product and circuit robustness.Leads in the development of hardware and system level specifications of moderate complexity.Writes and reviews test plans, executes or supervises testing, evaluates and reviews test results for use in peer reviews and for project notebooks.Prepares and maintains accurate p

Full-time

USD 129,200.00 - 193,900.00 per year

Verification Engineer

Saratoga, California

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26d ago

Qualifications ME/BE in Electrical Engineering, Computer Engineering, or related field.Experience:A MINIMUM of8-15 years in ASIC verification in the area of data center networking.Verification Skills: Expertise in Hardware Verification and Hardware Verification Methodology (e.g., System Verilog, OVM/VMM/UVM) with a strong understanding of ASIC Design and Verification flow. Experience with functional coverage, gate/timing/power simulations, constrained random verification and test-plan documentat

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Full-time

150000 - 200,000