Verilog jobs

San Jose, California

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Today

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the wo

Full-time

USD 139,860.00 per year

Senior FPGA Design Engineer (Hybrid-Puerto Rico)

Remote or Aguadilla, Aguadilla

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Today

Date Posted: 2026-01-08 Country: United States of America Location: HPR01: Collins Puerto Rico- Aguadilla Road 110 North Km 28.8 San Antonio Industrial Park, Aguadilla, PR, 00603 USA Position Role Type: Hybrid U.S. Citizen, U.S. Person, or Immigration Status Requirements: Security Clearance: None/Not Required Do you want to be a part of something bigger? A team whose impact stretches across the world, and even beyond? At Collins Aerospace, our Mission Systems team helps civilian, military and

Full-time

Senior Staff Engineer - SerDes Digital Design

Hudson, New York

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Today

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and be

Full-time

USD 125,900.00 - 186,260.00 per year

Principal Electrical Engineer - ASIC/FPGA (Onsite)

Salt Lake City, Utah

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Today

Date Posted: 2025-10-08 Country: United States of America Location: HUT31: Salt Lake City, UT 600 Komas Drive , Salt Lake City, UT, 84108-1229 USA Position Role Type: Onsite U.S. Citizen, U.S. Person, or Immigration Status Requirements: The ability to obtain and maintain a U.S. government issued security clearance is required.Security Clearance: DoD Clearance: Secret Principal Electrical Engineer - ASIC/FPGA (Onsite) This position is for a motivated Principal Electrical or Computer engineeri

Full-time

USD 101,000.00 per year

Design Verification Engineer

San Diego, California

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6d ago

Job Title:DesignVerificationEngineerLocation:San Diego, CAExperience Level: 7+ YearsJob Description:We are seeking a skilledDesignVerificationEngineerwith strong expertise in System Verilog (SV) and UVM methodologies to join our team. The ideal candidate will have hands-on experience in developing, updating, and debuggingverificationtestbenches, with the ability to integrateVerificationIPs (VIPs) orDesignIPs into theverificationenvironment.Responsibilities:Develop, enhance, and debug System Veri

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Contract, Third Party

180,000 - 200,000

FPGA Verification Engineer

Mountain View, California

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7d ago

FPGA Verification Engineer Mountain View, CA Job Description Strong understanding of FPGA design principles and architectures.Proficiency in System Verilog and UVM verification methodology.Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS).Knowledge of code coverage and functional coverage analysis.Excellent debugging and problem-solving skills.Strong communication and collaboration skills. Requirements Bachelor s or master s degree in electrical engineering, C

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Third Party, Contract

Depends on Experience

Design Verification Engineer

Sunnyvale, California

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2d ago

Hi, Full Time / Permanent Role Role: Design Verification Engineer Location : Sunnyvale CA / Austin TX Candidates with AXI and PCIE or Ethernet or DDR experience. Scripting is a plus Strong understanding of SV and UVM and good debugging skills. Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing

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Full-time

Depends on Experience

FPGA/Design/Hardware Verification

Mountain View, California

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2d ago

Job Title: FPGA/Design Verification Engineer Location: Mountain View, CA (Onsite)Duration: 12+ MonthsJob Description Strong understanding of FPGA design principles and architectures. Proficiency in System Verilog and UVM verification methodology. Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS). Knowledge of code coverage and functional coverage analysis. Excellent debugging and problem-solving skills. Strong communication and collaboration skills. Requ

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Contract, Third Party

Depends on Experience

FPGA Verification Engineer

Santa Clara, California

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Today

Job Title: FPGA Verification Engineer Location: Santa Clara, CA-Onsite 100%, Day 1 Mon-Fri Duration: 12+ Months Mandatory Areas Must Have Skills FPGA Verification Engineer Skill 1 8 + Years of in FPGA Skill 2 5 +Years of Exp in UVM Skill 2 5 +Years of Exp in System Verlilog Job Description: Strong understanding of FPGA design principles and architectures. Proficiency in System Verilog and UVM verification methodology. Experience with industry-standard verification tools (e.g., Questa

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Contract, Third Party

FPGA Verification Engineer

Santa Clara, California

•

Today

FPGA Verification Engineer Santa Clara, CA- 5days onsite Mandatory Areas Must Have Skills FPGA Verification Engineer Skill 1 8 + Years of in FPGA Skill 2 5 +Years of Exp in UVM Skill 2 5 +Years of Exp in System Verlilog Job Description: We are seeking a highly motivated and skilled FPGA Verification Engineer to join our dynamic team. In this role, you will be responsible for the verification of complex FPGA designs, ensuring their functionality, performance, and reliability. You will work

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Full-time, Third Party, Contract

Design Verification Engineer

San Jose, California

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10d ago

Role: Design Verification Engineer Location: San Jose CA/ Irvine CA / San Diego CA Job Description:Experience: 6 to 15+ years of experience. Job Requirements are as below: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM Debug RTL and Gate simula

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Full-time

Depends on Experience

IC Verification Engineer

San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Job duties include: Develop Test plans for all features for Block/Core/SOC and Write Functional coverage for these features.Architect and develop scalable and re-usable testbenches, using the framework of the verification methodologyBuild pseudo-random

Full-time

USD 120,000.00 - 192,000.00 per year

FPGA / RTL Design Engineer

California

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Today

Job Title: FPGA / RTL Design Engineer Location: San Jose, CA Job Description: FPGA/RTL Design Engineer to design, implement, and validate digital circuits and FPGA-based solutions. This role involves hands-on development using RTL languages, FPGA design tools, and simulation environments, while also supporting customers and creating technical assets that enable successful adoption of our products. Key Responsibilities Design & Implementation: Develop RTL code (Verilog, VHDL, SystemVerilog) for

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Contract, Third Party

Design Verification Engineer (GPU)

San Jose, California

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Today

Job Description Onsite, 5 days a week in San Jose Role and Responsibilities: Key responsibilities include Work with architects and designers to build verification environments and test plans Craft functional verification coverage strategy to ensure complete test suite implementation Develop assertions and checks to optimize isolation time and produce meaningful failing signatures Analyze failing tests to root cause along, working with RTL and reference modeling teams Provide input on Architectu

Contract

Engineer, Senior Staff

Santa Clara, California

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Today

JOB DESCRIPTION Top 5 Required Skills 1. Expert experience in C++ Programming Language 2. Hands on experience with System Verilog 3. Knowledge in AI ML (Artificial Intelligence Machine Learning) 4. Experience with software productization 5. Documentation, Debugging and Developer experience Technologies: C++ Programming Language System Verilog SIC Required Education: . Bachelors Degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, v

Full-time

RISCV CPU Systems Architecture/RTL Engineer - Senior Level

Santa Clara, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: We are hiring talented engineers for RISCV CPU RTL development targeting high-performance, low-power devices. In this role, you will contribute to architecture and product definition and be responsible for microarchitecture and RTL execution of CPU system features. These include, but are not limited to: System architecture - configuration access protocols and ordering require

Full-time

USD 198,700.00 - 298,100.00 per year

Electrical Engineer Senior

Hybrid in Lincolnshire, Illinois

•

Yesterday

Electrical Engineer Senior Duration 6 months Location- Hybrid 3 days a week in Lincolnshire, IllinoisPotential contract to hire Designs, develops, modifies and evaluates components and processes used in the generation, manipulation, transmission and storage of electricity. Determines design approaches and parameters. Analyzes equipment to establish operating data and conducts experiments. Responsibilities: Read and design plans to build electrical systems on a variety of products and machiner

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Contract

Up to $55

FPGA Design / Verification Engineer

Englewood, Colorado

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8d ago

Job Title: FPGA Design/Verification Engineer Duration: up to 6 months contract with possible extension Location: Littleton, CO Work Schedule: 5/10 1st Shift, Monday to Friday; 8 hours per day. Pay Rate: $100/hr on W2 [the pay rate may differ depending on your skills, education, experience, and other qualifications] Featured Benefits: Medical Insurance in compliance with the ACA 401(k) Sick leave in compliance with applicable state, federal, and local laws Job Description: The selected can

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Contract

100

ASIC Power engineer, or CAD Engineer/Physical Design engineer // Sunnyvale, CA

No location provided

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6d ago

ASIC Power Engineer Sunnyvale, CA Duties: ASIC Power Engineer to perform power analysis and optimizations in ASIC for Meta's AR/VR products. Areas of interests includes Machine Learning. Primary languages are Python, TCL and System Verilog. Responsibilities Perform PPA optimization with Fusion compiler. Perform RTL and netlist level Power analysis Perform post-processing and scripting on report log files for format conversion, data analysis and information extraction Setup, run, debug and analy

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Third Party, Contract

GPU Design Verification Engineer

San Jose, California

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14d ago

Job Title- GPU Design Verification Engineer Duration- 06+ Months with Possible extension Location San Jose CA(Onsite) Description As a GPU Design Verification Engineer, your talents will ensure the quality at the heart of our GPU architecture. Creativity is a necessity to overcome the challenges inherent to verifying the proper operation of our low-power GPU. Versatility and broad knowledge of state-of-the-art verification techniques including the most up-to-date I UVM version will place you amo

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Contract

$75 - $85

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